John Crispin 69ebed7dc9 MIPS: ralink: Add missing clock on rt305x ... The rt305x support is missing a clock required by the ethernet driver. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11447/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-11-11 08:38:15 +01:00
..
bootrom.c
cevt-rt3352.c	MIPS: ralink: Fix invalid tick count	2015-11-11 08:38:04 +01:00
clk.c
common.h
early_printk.c	MIPS: ralink: Add tty detection	2015-11-11 08:38:03 +01:00
ill_acc.c
irq.c
Kconfig
Makefile
mt7620.c	MIPS: ralink: Remove check for CONFIG_PCI on non-PCI SoCs	2015-11-11 08:38:10 +01:00
of.c
Platform
prom.c	MIPS: ralink: Unify SoC id handling	2015-11-11 08:37:56 +01:00
reset.c	MIPS: ralink: Put the pci bus into reset state before rebooting the SoC	2015-11-11 08:38:14 +01:00
rt288x.c	MIPS: ralink: Unify SoC id handling	2015-11-11 08:37:56 +01:00
rt305x.c	MIPS: ralink: Add missing clock on rt305x	2015-11-11 08:38:15 +01:00
rt3883.c	MIPS: ralink: Unify SoC id handling	2015-11-11 08:37:56 +01:00
timer.c