forked from luck/tmp_suning_uos_patched
a1be3cfdfb
Tegra114 doesn't have SATA nor PCIe, but TRM seems erroneously document them. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
44 lines
1.2 KiB
C
44 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA114_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA114_MC_H
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_EPP 3
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#define TEGRA_SWGROUP_G2 4
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#define TEGRA_SWGROUP_AVPC 5
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#define TEGRA_SWGROUP_NV 6
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#define TEGRA_SWGROUP_HDA 7
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#define TEGRA_SWGROUP_HC 8
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#define TEGRA_SWGROUP_MSENC 9
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#define TEGRA_SWGROUP_PPCS 10
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#define TEGRA_SWGROUP_VDE 11
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#define TEGRA_SWGROUP_MPCORELP 12
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#define TEGRA_SWGROUP_MPCORE 13
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#define TEGRA_SWGROUP_VI 14
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#define TEGRA_SWGROUP_ISP 15
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#define TEGRA_SWGROUP_XUSB_HOST 16
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#define TEGRA_SWGROUP_XUSB_DEV 17
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#define TEGRA_SWGROUP_EMUCIF 18
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#define TEGRA_SWGROUP_TSEC 19
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#define TEGRA114_MC_RESET_AVPC 0
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#define TEGRA114_MC_RESET_DC 1
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#define TEGRA114_MC_RESET_DCB 2
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#define TEGRA114_MC_RESET_EPP 3
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#define TEGRA114_MC_RESET_2D 4
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#define TEGRA114_MC_RESET_HC 5
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#define TEGRA114_MC_RESET_HDA 6
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#define TEGRA114_MC_RESET_ISP 7
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#define TEGRA114_MC_RESET_MPCORE 8
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#define TEGRA114_MC_RESET_MPCORELP 9
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#define TEGRA114_MC_RESET_MPE 10
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#define TEGRA114_MC_RESET_3D 11
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#define TEGRA114_MC_RESET_3D2 12
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#define TEGRA114_MC_RESET_PPCS 13
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#define TEGRA114_MC_RESET_VDE 14
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#define TEGRA114_MC_RESET_VI 15
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#endif
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