kernel_optimize_test/arch/arm/boot/compressed
Will Deacon d675d0bc47 ARM: LPAE: add ISBs around MMU enabling code
Before we enable the MMU, we must ensure that the TTBR registers contain
sane values. After the MMU has been enabled, we jump to the *virtual*
address of the following function, so we also need to ensure that the
SCTLR write has taken effect.

This patch adds ISB instructions around the SCTLR write to ensure the
visibility of the above.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2011-12-08 10:30:38 +00:00
..
.gitignore
atags_to_fdt.c
big-endian.S
decompress.c
head-sa1100.S
head-shark.S
head-sharpsl.S
head-shmobile.S
head-vt8500.S
head-xscale.S
head.S
libfdt_env.h
ll_char_wr.S
Makefile
misc.c
mmcif-sh7372.c
ofw-shark.c
piggy.gzip.S
piggy.lzma.S
piggy.lzo.S
sdhi-sh7372.c
sdhi-shmobile.c
sdhi-shmobile.h
string.c
vmlinux.lds.in