forked from luck/tmp_suning_uos_patched
dffa91539e
Drivers that do not support the PCI error handling callbacks are handled by
tearing down the device and re-probing them. If the device being removed is
a virtual function then we need to know the VF index so it can be removed
using the pci_iov_{add|remove}_virtfn() API.
Currently this is handled by looking up the pci_dn, and using the vf_index
that was stashed there when the pci_dn for the VF was created in
pcibios_sriov_enable(). We would like to eliminate the use of pci_dn
outside of pseries though so we need to provide the generic EEH code with
some other way to find the vf_index.
The easiest thing to do here is move the vf_index field out of pci_dn and
into eeh_dev. Currently pci_dn and eeh_dev are allocated and initialized
together so this is a fairly minimal change in preparation for splitting
pci_dn and eeh_dev in the future.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200725081231.39076-3-oohall@gmail.com
299 lines
9.2 KiB
C
299 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _ASM_POWERPC_PCI_BRIDGE_H
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#define _ASM_POWERPC_PCI_BRIDGE_H
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#ifdef __KERNEL__
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/*
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*/
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#include <linux/pci.h>
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#include <linux/list.h>
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#include <linux/ioport.h>
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#include <linux/numa.h>
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struct device_node;
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/*
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* PCI controller operations
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*/
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struct pci_controller_ops {
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void (*dma_dev_setup)(struct pci_dev *pdev);
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void (*dma_bus_setup)(struct pci_bus *bus);
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bool (*iommu_bypass_supported)(struct pci_dev *pdev,
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u64 mask);
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int (*probe_mode)(struct pci_bus *bus);
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/* Called when pci_enable_device() is called. Returns true to
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* allow assignment/enabling of the device. */
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bool (*enable_device_hook)(struct pci_dev *pdev);
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void (*disable_device)(struct pci_dev *pdev);
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void (*release_device)(struct pci_dev *pdev);
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/* Called during PCI resource reassignment */
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resource_size_t (*window_alignment)(struct pci_bus *bus,
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unsigned long type);
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void (*setup_bridge)(struct pci_bus *bus,
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unsigned long type);
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void (*reset_secondary_bus)(struct pci_dev *pdev);
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#ifdef CONFIG_PCI_MSI
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int (*setup_msi_irqs)(struct pci_dev *pdev,
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int nvec, int type);
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void (*teardown_msi_irqs)(struct pci_dev *pdev);
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#endif
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void (*shutdown)(struct pci_controller *hose);
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};
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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struct pci_bus *bus;
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char is_dynamic;
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#ifdef CONFIG_PPC64
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int node;
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#endif
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struct device_node *dn;
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struct list_head list_node;
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struct device *parent;
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int first_busno;
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int last_busno;
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int self_busno;
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struct resource busn;
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void __iomem *io_base_virt;
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#ifdef CONFIG_PPC64
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void __iomem *io_base_alloc;
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#endif
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resource_size_t io_base_phys;
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resource_size_t pci_io_size;
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/* Some machines have a special region to forward the ISA
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* "memory" cycles such as VGA memory regions. Left to 0
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* if unsupported
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*/
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resource_size_t isa_mem_phys;
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resource_size_t isa_mem_size;
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struct pci_controller_ops controller_ops;
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struct pci_ops *ops;
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unsigned int __iomem *cfg_addr;
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void __iomem *cfg_data;
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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* EXT_REG - provides access to PCI-e extended registers
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* SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS
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* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
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* to determine which bus number to match on when generating type0
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* config cycles
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* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
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* hanging if we don't have link and try to do config cycles to
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* anything but the PHB. Only allow talking to the PHB if this is
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* set.
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* BIG_ENDIAN - cfg_addr is a big endian register
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* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
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* the PLB4. Effectively disable MRM commands by setting this.
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* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
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* link status is in a RC PCIe cfg register (vs being a SoC register)
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
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#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
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#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
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#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
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#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
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u32 indirect_type;
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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struct resource io_resource;
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struct resource mem_resources[3];
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resource_size_t mem_offset[3];
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int global_number; /* PCI domain number */
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resource_size_t dma_window_base_cur;
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resource_size_t dma_window_size;
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#ifdef CONFIG_PPC64
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unsigned long buid;
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struct pci_dn *pci_data;
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#endif /* CONFIG_PPC64 */
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void *private_data;
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struct npu *npu;
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};
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/* These are used for config access before all the PCI probing
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has been done. */
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extern int early_read_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 *val);
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extern int early_read_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 *val);
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extern int early_read_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 *val);
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extern int early_write_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 val);
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extern int early_write_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 val);
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extern int early_write_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 val);
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extern int early_find_capability(struct pci_controller *hose, int bus,
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int dev_fn, int cap);
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extern void setup_indirect_pci(struct pci_controller* hose,
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resource_size_t cfg_addr,
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resource_size_t cfg_data, u32 flags);
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extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 *val);
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extern int __indirect_read_config(struct pci_controller *hose,
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unsigned char bus_number, unsigned int devfn,
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int offset, int len, u32 *val);
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extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
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int offset, int len, u32 val);
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static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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#ifndef CONFIG_PPC64
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extern int pci_device_from_OF_node(struct device_node *node,
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u8 *bus, u8 *devfn);
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extern void pci_create_OF_bus_map(void);
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#else /* CONFIG_PPC64 */
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/*
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* PCI stuff, for nodes representing PCI devices, pointed to
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* by device_node->data.
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*/
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struct iommu_table;
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struct pci_dn {
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int flags;
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#define PCI_DN_FLAG_IOV_VF 0x01
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#define PCI_DN_FLAG_DEAD 0x02 /* Device has been hot-removed */
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int busno; /* pci bus number */
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int devfn; /* pci device and function number */
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int vendor_id; /* Vendor ID */
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int device_id; /* Device ID */
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int class_code; /* Device class code */
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struct pci_dn *parent;
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struct pci_controller *phb; /* for pci devices */
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struct iommu_table_group *table_group; /* for phb's or bridges */
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int pci_ext_config_space; /* for pci devices */
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#ifdef CONFIG_EEH
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struct eeh_dev *edev; /* eeh device */
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#endif
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#define IODA_INVALID_PE 0xFFFFFFFF
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unsigned int pe_number;
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#ifdef CONFIG_PCI_IOV
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u16 vfs_expanded; /* number of VFs IOV BAR expanded */
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u16 num_vfs; /* number of VFs enabled*/
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unsigned int *pe_num_map; /* PE# for the first VF PE or array */
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bool m64_single_mode; /* Use M64 BAR in Single Mode */
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#define IODA_INVALID_M64 (-1)
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int (*m64_map)[PCI_SRIOV_NUM_BARS]; /* Only used on powernv */
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int last_allow_rc; /* Only used on pseries */
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#endif /* CONFIG_PCI_IOV */
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int mps; /* Maximum Payload Size */
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struct list_head child_list;
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struct list_head list;
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struct resource holes[PCI_SRIOV_NUM_BARS];
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};
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/* Get the pointer to a device_node's pci_dn */
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#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
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extern struct pci_dn *pci_get_pdn_by_devfn(struct pci_bus *bus,
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int devfn);
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extern struct pci_dn *pci_get_pdn(struct pci_dev *pdev);
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extern struct pci_dn *pci_add_device_node_info(struct pci_controller *hose,
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struct device_node *dn);
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extern void pci_remove_device_node_info(struct device_node *dn);
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#ifdef CONFIG_PCI_IOV
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struct pci_dn *add_sriov_vf_pdns(struct pci_dev *pdev);
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void remove_sriov_vf_pdns(struct pci_dev *pdev);
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#endif
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static inline int pci_device_from_OF_node(struct device_node *np,
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u8 *bus, u8 *devfn)
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{
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if (!PCI_DN(np))
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return -ENODEV;
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*bus = PCI_DN(np)->busno;
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*devfn = PCI_DN(np)->devfn;
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return 0;
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}
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#if defined(CONFIG_EEH)
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static inline struct eeh_dev *pdn_to_eeh_dev(struct pci_dn *pdn)
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{
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return pdn ? pdn->edev : NULL;
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}
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#else
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#define pdn_to_eeh_dev(x) (NULL)
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#endif
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/** Find the bus corresponding to the indicated device node */
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extern struct pci_bus *pci_find_bus_by_node(struct device_node *dn);
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/** Remove all of the PCI devices under this bus */
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extern void pci_hp_remove_devices(struct pci_bus *bus);
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/** Discover new pci devices under this bus, and add them */
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extern void pci_hp_add_devices(struct pci_bus *bus);
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extern int pcibios_unmap_io_space(struct pci_bus *bus);
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extern int pcibios_map_io_space(struct pci_bus *bus);
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#ifdef CONFIG_NUMA
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#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
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#else
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#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = NUMA_NO_NODE)
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#endif
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#endif /* CONFIG_PPC64 */
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/* Get the PCI host controller for an OF device */
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extern struct pci_controller *pci_find_hose_for_OF_device(
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struct device_node* node);
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extern struct pci_controller *pci_find_controller_for_domain(int domain_nr);
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/* Fill up host controller resources from the OF node */
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extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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/* Allocate & free a PCI host bridge structure */
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extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
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extern void pcibios_free_controller(struct pci_controller *phb);
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extern void pcibios_free_controller_deferred(struct pci_host_bridge *bridge);
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#ifdef CONFIG_PCI
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extern int pcibios_vaddr_is_ioport(void __iomem *address);
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#else
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static inline int pcibios_vaddr_is_ioport(void __iomem *address)
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{
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return 0;
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}
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#endif /* CONFIG_PCI */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
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