forked from luck/tmp_suning_uos_patched
6ecba8eb51
Recently, the default DMA ops have been changed to non-coherent for alignment with 32-bit ARM platforms (and DT files). This patch adds bus notifiers to be able to set the coherent DMA ops (with no cache maintenance) for devices explicitly marked as coherent via the "dma-coherent" DT property. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
488 lines
12 KiB
C
488 lines
12 KiB
C
/*
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* Based on arch/arm/kernel/setup.c
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*
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* Copyright (C) 1995-2001 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/utsname.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/screen_info.h>
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#include <linux/init.h>
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#include <linux/kexec.h>
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#include <linux/crash_dump.h>
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#include <linux/root_dev.h>
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#include <linux/clk-provider.h>
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#include <linux/cpu.h>
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#include <linux/interrupt.h>
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#include <linux/smp.h>
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#include <linux/fs.h>
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#include <linux/proc_fs.h>
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#include <linux/memblock.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/fixmap.h>
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#include <asm/cputype.h>
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#include <asm/elf.h>
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#include <asm/cputable.h>
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#include <asm/cpu_ops.h>
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#include <asm/sections.h>
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#include <asm/setup.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/traps.h>
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#include <asm/memblock.h>
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#include <asm/psci.h>
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unsigned int processor_id;
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EXPORT_SYMBOL(processor_id);
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unsigned long elf_hwcap __read_mostly;
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EXPORT_SYMBOL_GPL(elf_hwcap);
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#ifdef CONFIG_COMPAT
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#define COMPAT_ELF_HWCAP_DEFAULT \
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(COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
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COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
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COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
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COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
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COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV)
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unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
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unsigned int compat_elf_hwcap2 __read_mostly;
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#endif
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static const char *cpu_name;
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static const char *machine_name;
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phys_addr_t __fdt_pointer __initdata;
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/*
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* Standard memory resources
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*/
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static struct resource mem_res[] = {
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{
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.name = "Kernel code",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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},
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{
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.name = "Kernel data",
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.start = 0,
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.end = 0,
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.flags = IORESOURCE_MEM
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}
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};
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#define kernel_code mem_res[0]
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#define kernel_data mem_res[1]
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void __init early_print(const char *str, ...)
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{
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char buf[256];
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va_list ap;
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va_start(ap, str);
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vsnprintf(buf, sizeof(buf), str, ap);
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va_end(ap);
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printk("%s", buf);
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}
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void __init smp_setup_processor_id(void)
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{
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/*
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* clear __my_cpu_offset on boot CPU to avoid hang caused by
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* using percpu variable early, for example, lockdep will
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* access percpu variable inside lock_release
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*/
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set_my_cpu_offset(0);
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}
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bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
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{
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return phys_id == cpu_logical_map(cpu);
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}
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struct mpidr_hash mpidr_hash;
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#ifdef CONFIG_SMP
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/**
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* smp_build_mpidr_hash - Pre-compute shifts required at each affinity
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* level in order to build a linear index from an
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* MPIDR value. Resulting algorithm is a collision
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* free hash carried out through shifting and ORing
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*/
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static void __init smp_build_mpidr_hash(void)
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{
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u32 i, affinity, fs[4], bits[4], ls;
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u64 mask = 0;
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/*
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* Pre-scan the list of MPIDRS and filter out bits that do
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* not contribute to affinity levels, ie they never toggle.
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*/
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for_each_possible_cpu(i)
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mask |= (cpu_logical_map(i) ^ cpu_logical_map(0));
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pr_debug("mask of set bits %#llx\n", mask);
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/*
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* Find and stash the last and first bit set at all affinity levels to
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* check how many bits are required to represent them.
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*/
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for (i = 0; i < 4; i++) {
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affinity = MPIDR_AFFINITY_LEVEL(mask, i);
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/*
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* Find the MSB bit and LSB bits position
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* to determine how many bits are required
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* to express the affinity level.
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*/
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ls = fls(affinity);
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fs[i] = affinity ? ffs(affinity) - 1 : 0;
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bits[i] = ls - fs[i];
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}
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/*
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* An index can be created from the MPIDR_EL1 by isolating the
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* significant bits at each affinity level and by shifting
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* them in order to compress the 32 bits values space to a
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* compressed set of values. This is equivalent to hashing
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* the MPIDR_EL1 through shifting and ORing. It is a collision free
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* hash though not minimal since some levels might contain a number
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* of CPUs that is not an exact power of 2 and their bit
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* representation might contain holes, eg MPIDR_EL1[7:0] = {0x2, 0x80}.
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*/
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mpidr_hash.shift_aff[0] = MPIDR_LEVEL_SHIFT(0) + fs[0];
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mpidr_hash.shift_aff[1] = MPIDR_LEVEL_SHIFT(1) + fs[1] - bits[0];
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mpidr_hash.shift_aff[2] = MPIDR_LEVEL_SHIFT(2) + fs[2] -
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(bits[1] + bits[0]);
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mpidr_hash.shift_aff[3] = MPIDR_LEVEL_SHIFT(3) +
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fs[3] - (bits[2] + bits[1] + bits[0]);
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mpidr_hash.mask = mask;
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mpidr_hash.bits = bits[3] + bits[2] + bits[1] + bits[0];
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pr_debug("MPIDR hash: aff0[%u] aff1[%u] aff2[%u] aff3[%u] mask[%#llx] bits[%u]\n",
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mpidr_hash.shift_aff[0],
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mpidr_hash.shift_aff[1],
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mpidr_hash.shift_aff[2],
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mpidr_hash.shift_aff[3],
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mpidr_hash.mask,
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mpidr_hash.bits);
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/*
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* 4x is an arbitrary value used to warn on a hash table much bigger
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* than expected on most systems.
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*/
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if (mpidr_hash_size() > 4 * num_possible_cpus())
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pr_warn("Large number of MPIDR hash buckets detected\n");
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__flush_dcache_area(&mpidr_hash, sizeof(struct mpidr_hash));
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}
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#endif
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static void __init setup_processor(void)
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{
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struct cpu_info *cpu_info;
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u64 features, block;
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cpu_info = lookup_processor_type(read_cpuid_id());
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if (!cpu_info) {
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printk("CPU configuration botched (ID %08x), unable to continue.\n",
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read_cpuid_id());
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while (1);
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}
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cpu_name = cpu_info->cpu_name;
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printk("CPU: %s [%08x] revision %d\n",
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cpu_name, read_cpuid_id(), read_cpuid_id() & 15);
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sprintf(init_utsname()->machine, ELF_PLATFORM);
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elf_hwcap = 0;
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/*
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* ID_AA64ISAR0_EL1 contains 4-bit wide signed feature blocks.
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* The blocks we test below represent incremental functionality
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* for non-negative values. Negative values are reserved.
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*/
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features = read_cpuid(ID_AA64ISAR0_EL1);
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block = (features >> 4) & 0xf;
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if (!(block & 0x8)) {
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switch (block) {
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default:
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case 2:
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elf_hwcap |= HWCAP_PMULL;
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case 1:
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elf_hwcap |= HWCAP_AES;
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case 0:
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break;
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}
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}
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block = (features >> 8) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_SHA1;
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block = (features >> 12) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_SHA2;
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block = (features >> 16) & 0xf;
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if (block && !(block & 0x8))
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elf_hwcap |= HWCAP_CRC32;
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#ifdef CONFIG_COMPAT
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/*
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* ID_ISAR5_EL1 carries similar information as above, but pertaining to
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* the Aarch32 32-bit execution state.
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*/
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features = read_cpuid(ID_ISAR5_EL1);
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block = (features >> 4) & 0xf;
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if (!(block & 0x8)) {
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switch (block) {
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default:
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case 2:
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compat_elf_hwcap2 |= COMPAT_HWCAP2_PMULL;
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case 1:
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compat_elf_hwcap2 |= COMPAT_HWCAP2_AES;
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case 0:
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break;
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}
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}
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block = (features >> 8) & 0xf;
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if (block && !(block & 0x8))
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compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA1;
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block = (features >> 12) & 0xf;
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if (block && !(block & 0x8))
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compat_elf_hwcap2 |= COMPAT_HWCAP2_SHA2;
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block = (features >> 16) & 0xf;
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if (block && !(block & 0x8))
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compat_elf_hwcap2 |= COMPAT_HWCAP2_CRC32;
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#endif
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}
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static void __init setup_machine_fdt(phys_addr_t dt_phys)
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{
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if (!dt_phys || !early_init_dt_scan(phys_to_virt(dt_phys))) {
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early_print("\n"
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"Error: invalid device tree blob at physical address 0x%p (virtual address 0x%p)\n"
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"The dtb must be 8-byte aligned and passed in the first 512MB of memory\n"
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"\nPlease check your bootloader.\n",
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dt_phys, phys_to_virt(dt_phys));
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while (true)
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cpu_relax();
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}
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machine_name = of_flat_dt_get_machine_name();
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}
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/*
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* Limit the memory size that was specified via FDT.
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*/
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static int __init early_mem(char *p)
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{
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phys_addr_t limit;
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if (!p)
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return 1;
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limit = memparse(p, &p) & PAGE_MASK;
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pr_notice("Memory limited to %lldMB\n", limit >> 20);
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memblock_enforce_memory_limit(limit);
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return 0;
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}
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early_param("mem", early_mem);
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static void __init request_standard_resources(void)
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{
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struct memblock_region *region;
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struct resource *res;
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kernel_code.start = virt_to_phys(_text);
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kernel_code.end = virt_to_phys(_etext - 1);
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kernel_data.start = virt_to_phys(_sdata);
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kernel_data.end = virt_to_phys(_end - 1);
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for_each_memblock(memory, region) {
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res = alloc_bootmem_low(sizeof(*res));
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res->name = "System RAM";
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res->start = __pfn_to_phys(memblock_region_memory_base_pfn(region));
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res->end = __pfn_to_phys(memblock_region_memory_end_pfn(region)) - 1;
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res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
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request_resource(&iomem_resource, res);
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if (kernel_code.start >= res->start &&
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kernel_code.end <= res->end)
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request_resource(res, &kernel_code);
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if (kernel_data.start >= res->start &&
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kernel_data.end <= res->end)
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request_resource(res, &kernel_data);
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}
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}
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u64 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = INVALID_HWID };
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void __init setup_arch(char **cmdline_p)
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{
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/*
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* Unmask asynchronous aborts early to catch possible system errors.
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*/
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local_async_enable();
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setup_processor();
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setup_machine_fdt(__fdt_pointer);
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init_mm.start_code = (unsigned long) _text;
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init_mm.end_code = (unsigned long) _etext;
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init_mm.end_data = (unsigned long) _edata;
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init_mm.brk = (unsigned long) _end;
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*cmdline_p = boot_command_line;
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init_mem_pgprot();
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early_ioremap_init();
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parse_early_param();
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arm64_memblock_init();
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paging_init();
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request_standard_resources();
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unflatten_device_tree();
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psci_init();
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cpu_logical_map(0) = read_cpuid_mpidr() & MPIDR_HWID_BITMASK;
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cpu_read_bootcpu_ops();
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#ifdef CONFIG_SMP
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smp_init_cpus();
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smp_build_mpidr_hash();
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#endif
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#ifdef CONFIG_VT
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#if defined(CONFIG_VGA_CONSOLE)
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conswitchp = &vga_con;
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#elif defined(CONFIG_DUMMY_CONSOLE)
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conswitchp = &dummy_con;
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#endif
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#endif
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}
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static int __init arm64_device_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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return 0;
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}
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arch_initcall_sync(arm64_device_init);
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static DEFINE_PER_CPU(struct cpu, cpu_data);
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static int __init topology_init(void)
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{
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int i;
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for_each_possible_cpu(i) {
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struct cpu *cpu = &per_cpu(cpu_data, i);
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cpu->hotpluggable = 1;
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register_cpu(cpu, i);
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}
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return 0;
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}
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subsys_initcall(topology_init);
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static const char *hwcap_str[] = {
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"fp",
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"asimd",
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"evtstrm",
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"aes",
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"pmull",
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"sha1",
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"sha2",
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"crc32",
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NULL
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};
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static int c_show(struct seq_file *m, void *v)
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{
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int i;
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seq_printf(m, "Processor\t: %s rev %d (%s)\n",
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cpu_name, read_cpuid_id() & 15, ELF_PLATFORM);
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for_each_online_cpu(i) {
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/*
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* glibc reads /proc/cpuinfo to determine the number of
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* online processors, looking for lines beginning with
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* "processor". Give glibc what it expects.
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*/
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#ifdef CONFIG_SMP
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seq_printf(m, "processor\t: %d\n", i);
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#endif
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}
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/* dump out the processor features */
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seq_puts(m, "Features\t: ");
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for (i = 0; hwcap_str[i]; i++)
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if (elf_hwcap & (1 << i))
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seq_printf(m, "%s ", hwcap_str[i]);
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seq_printf(m, "\nCPU implementer\t: 0x%02x\n", read_cpuid_id() >> 24);
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seq_printf(m, "CPU architecture: AArch64\n");
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seq_printf(m, "CPU variant\t: 0x%x\n", (read_cpuid_id() >> 20) & 15);
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seq_printf(m, "CPU part\t: 0x%03x\n", (read_cpuid_id() >> 4) & 0xfff);
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seq_printf(m, "CPU revision\t: %d\n", read_cpuid_id() & 15);
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seq_puts(m, "\n");
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seq_printf(m, "Hardware\t: %s\n", machine_name);
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return 0;
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}
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static void *c_start(struct seq_file *m, loff_t *pos)
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{
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return *pos < 1 ? (void *)1 : NULL;
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}
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static void *c_next(struct seq_file *m, void *v, loff_t *pos)
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{
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++*pos;
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return NULL;
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}
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static void c_stop(struct seq_file *m, void *v)
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{
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}
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const struct seq_operations cpuinfo_op = {
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.start = c_start,
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.next = c_next,
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.stop = c_stop,
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.show = c_show
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};
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