forked from luck/tmp_suning_uos_patched
2066aadd53
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/sparc uses of the __cpuinit macros from
C files and removes __CPUINIT from assembly files. Note that even
though arch/sparc/kernel/trampoline_64.S has instances of ".previous"
in it, they are all paired off against explicit ".section" directives,
and not implicitly paired with __CPUINIT (unlike mips and arm were).
[1] https://lkml.org/lkml/2013/5/20/589
Cc: "David S. Miller" <davem@davemloft.net>
Cc: sparclinux@vger.kernel.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
202 lines
3.8 KiB
ArmAsm
202 lines
3.8 KiB
ArmAsm
/*
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* trampoline.S: SMP cpu boot-up trampoline code.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/init.h>
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#include <asm/head.h>
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#include <asm/psr.h>
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#include <asm/page.h>
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#include <asm/asi.h>
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#include <asm/ptrace.h>
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#include <asm/vaddrs.h>
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#include <asm/contregs.h>
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#include <asm/thread_info.h>
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.globl sun4m_cpu_startup
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.globl sun4d_cpu_startup
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.align 4
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/* When we start up a cpu for the first time it enters this routine.
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* This initializes the chip from whatever state the prom left it
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* in and sets PIL in %psr to 15, no irqs.
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*/
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sun4m_cpu_startup:
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cpu1_startup:
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sethi %hi(trapbase_cpu1), %g3
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b 1f
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or %g3, %lo(trapbase_cpu1), %g3
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cpu2_startup:
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sethi %hi(trapbase_cpu2), %g3
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b 1f
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or %g3, %lo(trapbase_cpu2), %g3
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cpu3_startup:
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sethi %hi(trapbase_cpu3), %g3
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b 1f
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or %g3, %lo(trapbase_cpu3), %g3
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1:
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/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
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set (PSR_PIL | PSR_S | PSR_PS), %g1
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wr %g1, 0x0, %psr ! traps off though
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WRITE_PAUSE
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/* Our %wim is one behind CWP */
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mov 2, %g1
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wr %g1, 0x0, %wim
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WRITE_PAUSE
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/* This identifies "this cpu". */
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wr %g3, 0x0, %tbr
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WRITE_PAUSE
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/* Give ourselves a stack and curptr. */
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set current_set, %g5
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srl %g3, 10, %g4
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and %g4, 0xc, %g4
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ld [%g5 + %g4], %g6
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sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
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or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
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add %g6, %sp, %sp
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/* Turn on traps (PSR_ET). */
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rd %psr, %g1
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wr %g1, PSR_ET, %psr ! traps on
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WRITE_PAUSE
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/* Init our caches, etc. */
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set poke_srmmu, %g5
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ld [%g5], %g5
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call %g5
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nop
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/* Start this processor. */
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call smp_callin
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nop
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b,a smp_panic
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.text
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.align 4
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smp_panic:
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call cpu_panic
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nop
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/* CPUID in bootbus can be found at PA 0xff0140000 */
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#define SUN4D_BOOTBUS_CPUID 0xf0140000
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.align 4
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sun4d_cpu_startup:
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/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
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set (PSR_PIL | PSR_S | PSR_PS), %g1
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wr %g1, 0x0, %psr ! traps off though
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WRITE_PAUSE
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/* Our %wim is one behind CWP */
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mov 2, %g1
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wr %g1, 0x0, %wim
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WRITE_PAUSE
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/* Set tbr - we use just one trap table. */
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set trapbase, %g1
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wr %g1, 0x0, %tbr
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WRITE_PAUSE
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/* Get our CPU id out of bootbus */
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set SUN4D_BOOTBUS_CPUID, %g3
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lduba [%g3] ASI_M_CTL, %g3
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and %g3, 0xf8, %g3
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srl %g3, 3, %g1
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sta %g1, [%g0] ASI_M_VIKING_TMP1
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/* Give ourselves a stack and curptr. */
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set current_set, %g5
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srl %g3, 1, %g4
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ld [%g5 + %g4], %g6
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sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
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or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
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add %g6, %sp, %sp
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/* Turn on traps (PSR_ET). */
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rd %psr, %g1
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wr %g1, PSR_ET, %psr ! traps on
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WRITE_PAUSE
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/* Init our caches, etc. */
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set poke_srmmu, %g5
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ld [%g5], %g5
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call %g5
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nop
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/* Start this processor. */
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call smp_callin
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nop
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b,a smp_panic
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.align 4
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.global leon_smp_cpu_startup, smp_penguin_ctable
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leon_smp_cpu_startup:
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set smp_penguin_ctable,%g1
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ld [%g1+4],%g1
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srl %g1,4,%g1
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set 0x00000100,%g5 /* SRMMU_CTXTBL_PTR */
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sta %g1, [%g5] ASI_LEON_MMUREGS
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/* Set up a sane %psr -- PIL<0xf> S<0x1> PS<0x1> CWP<0x0> */
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set (PSR_PIL | PSR_S | PSR_PS), %g1
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wr %g1, 0x0, %psr ! traps off though
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WRITE_PAUSE
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/* Our %wim is one behind CWP */
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mov 2, %g1
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wr %g1, 0x0, %wim
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WRITE_PAUSE
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/* Set tbr - we use just one trap table. */
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set trapbase, %g1
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wr %g1, 0x0, %tbr
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WRITE_PAUSE
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/* Get our CPU id */
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rd %asr17,%g3
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/* Give ourselves a stack and curptr. */
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set current_set, %g5
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srl %g3, 28, %g4
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sll %g4, 2, %g4
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ld [%g5 + %g4], %g6
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sethi %hi(THREAD_SIZE - STACKFRAME_SZ), %sp
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or %sp, %lo(THREAD_SIZE - STACKFRAME_SZ), %sp
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add %g6, %sp, %sp
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/* Turn on traps (PSR_ET). */
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rd %psr, %g1
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wr %g1, PSR_ET, %psr ! traps on
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WRITE_PAUSE
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/* Init our caches, etc. */
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set poke_srmmu, %g5
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ld [%g5], %g5
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call %g5
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nop
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/* Start this processor. */
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call smp_callin
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nop
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b,a smp_panic
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