forked from luck/tmp_suning_uos_patched
2127435e57
* Kill dead codes * Rearrange irq chip handlers * Minimize defconfig Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
171 lines
5.1 KiB
C
171 lines
5.1 KiB
C
/*
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* Common definitions for TX3927/TX4927
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000 Toshiba Corporation
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*/
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#ifndef __ASM_TXX927_H
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#define __ASM_TXX927_H
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struct txx927_tmr_reg {
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volatile unsigned long tcr;
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volatile unsigned long tisr;
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volatile unsigned long cpra;
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volatile unsigned long cprb;
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volatile unsigned long itmr;
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volatile unsigned long unused0[3];
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volatile unsigned long ccdr;
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volatile unsigned long unused1[3];
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volatile unsigned long pgmr;
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volatile unsigned long unused2[3];
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volatile unsigned long wtmr;
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volatile unsigned long unused3[43];
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volatile unsigned long trr;
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};
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struct txx927_sio_reg {
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volatile unsigned long lcr;
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volatile unsigned long dicr;
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volatile unsigned long disr;
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volatile unsigned long cisr;
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volatile unsigned long fcr;
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volatile unsigned long flcr;
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volatile unsigned long bgr;
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volatile unsigned long tfifo;
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volatile unsigned long rfifo;
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};
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struct txx927_pio_reg {
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volatile unsigned long dout;
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volatile unsigned long din;
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volatile unsigned long dir;
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volatile unsigned long od;
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volatile unsigned long flag[2];
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volatile unsigned long pol;
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volatile unsigned long intc;
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volatile unsigned long maskcpu;
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volatile unsigned long maskext;
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};
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/*
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* TMR
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*/
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/* TMTCR : Timer Control */
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#define TXx927_TMTCR_TCE 0x00000080
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#define TXx927_TMTCR_CCDE 0x00000040
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#define TXx927_TMTCR_CRE 0x00000020
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#define TXx927_TMTCR_ECES 0x00000008
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#define TXx927_TMTCR_CCS 0x00000004
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#define TXx927_TMTCR_TMODE_MASK 0x00000003
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#define TXx927_TMTCR_TMODE_ITVL 0x00000000
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/* TMTISR : Timer Int. Status */
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#define TXx927_TMTISR_TPIBS 0x00000004
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#define TXx927_TMTISR_TPIAS 0x00000002
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#define TXx927_TMTISR_TIIS 0x00000001
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/* TMTITMR : Interval Timer Mode */
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#define TXx927_TMTITMR_TIIE 0x00008000
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#define TXx927_TMTITMR_TZCE 0x00000001
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/*
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* SIO
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*/
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/* SILCR : Line Control */
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#define TXx927_SILCR_SCS_MASK 0x00000060
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#define TXx927_SILCR_SCS_IMCLK 0x00000000
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#define TXx927_SILCR_SCS_IMCLK_BG 0x00000020
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#define TXx927_SILCR_SCS_SCLK 0x00000040
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#define TXx927_SILCR_SCS_SCLK_BG 0x00000060
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#define TXx927_SILCR_UEPS 0x00000010
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#define TXx927_SILCR_UPEN 0x00000008
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#define TXx927_SILCR_USBL_MASK 0x00000004
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#define TXx927_SILCR_USBL_1BIT 0x00000004
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#define TXx927_SILCR_USBL_2BIT 0x00000000
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#define TXx927_SILCR_UMODE_MASK 0x00000003
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#define TXx927_SILCR_UMODE_8BIT 0x00000000
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#define TXx927_SILCR_UMODE_7BIT 0x00000001
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/* SIDICR : DMA/Int. Control */
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#define TXx927_SIDICR_TDE 0x00008000
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#define TXx927_SIDICR_RDE 0x00004000
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#define TXx927_SIDICR_TIE 0x00002000
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#define TXx927_SIDICR_RIE 0x00001000
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#define TXx927_SIDICR_SPIE 0x00000800
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#define TXx927_SIDICR_CTSAC 0x00000600
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#define TXx927_SIDICR_STIE_MASK 0x0000003f
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#define TXx927_SIDICR_STIE_OERS 0x00000020
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#define TXx927_SIDICR_STIE_CTSS 0x00000010
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#define TXx927_SIDICR_STIE_RBRKD 0x00000008
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#define TXx927_SIDICR_STIE_TRDY 0x00000004
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#define TXx927_SIDICR_STIE_TXALS 0x00000002
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#define TXx927_SIDICR_STIE_UBRKD 0x00000001
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/* SIDISR : DMA/Int. Status */
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#define TXx927_SIDISR_UBRK 0x00008000
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#define TXx927_SIDISR_UVALID 0x00004000
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#define TXx927_SIDISR_UFER 0x00002000
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#define TXx927_SIDISR_UPER 0x00001000
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#define TXx927_SIDISR_UOER 0x00000800
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#define TXx927_SIDISR_ERI 0x00000400
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#define TXx927_SIDISR_TOUT 0x00000200
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#define TXx927_SIDISR_TDIS 0x00000100
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#define TXx927_SIDISR_RDIS 0x00000080
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#define TXx927_SIDISR_STIS 0x00000040
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#define TXx927_SIDISR_RFDN_MASK 0x0000001f
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/* SICISR : Change Int. Status */
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#define TXx927_SICISR_OERS 0x00000020
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#define TXx927_SICISR_CTSS 0x00000010
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#define TXx927_SICISR_RBRKD 0x00000008
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#define TXx927_SICISR_TRDY 0x00000004
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#define TXx927_SICISR_TXALS 0x00000002
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#define TXx927_SICISR_UBRKD 0x00000001
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/* SIFCR : FIFO Control */
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#define TXx927_SIFCR_SWRST 0x00008000
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#define TXx927_SIFCR_RDIL_MASK 0x00000180
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#define TXx927_SIFCR_RDIL_1 0x00000000
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#define TXx927_SIFCR_RDIL_4 0x00000080
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#define TXx927_SIFCR_RDIL_8 0x00000100
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#define TXx927_SIFCR_RDIL_12 0x00000180
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#define TXx927_SIFCR_RDIL_MAX 0x00000180
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#define TXx927_SIFCR_TDIL_MASK 0x00000018
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#define TXx927_SIFCR_TDIL_MASK 0x00000018
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#define TXx927_SIFCR_TDIL_1 0x00000000
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#define TXx927_SIFCR_TDIL_4 0x00000001
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#define TXx927_SIFCR_TDIL_8 0x00000010
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#define TXx927_SIFCR_TDIL_MAX 0x00000010
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#define TXx927_SIFCR_TFRST 0x00000004
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#define TXx927_SIFCR_RFRST 0x00000002
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#define TXx927_SIFCR_FRSTE 0x00000001
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#define TXx927_SIO_TX_FIFO 8
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#define TXx927_SIO_RX_FIFO 16
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/* SIFLCR : Flow Control */
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#define TXx927_SIFLCR_RCS 0x00001000
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#define TXx927_SIFLCR_TES 0x00000800
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#define TXx927_SIFLCR_RTSSC 0x00000200
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#define TXx927_SIFLCR_RSDE 0x00000100
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#define TXx927_SIFLCR_TSDE 0x00000080
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#define TXx927_SIFLCR_RTSTL_MASK 0x0000001e
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#define TXx927_SIFLCR_RTSTL_MAX 0x0000001e
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#define TXx927_SIFLCR_TBRK 0x00000001
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/* SIBGR : Baudrate Control */
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#define TXx927_SIBGR_BCLK_MASK 0x00000300
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#define TXx927_SIBGR_BCLK_T0 0x00000000
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#define TXx927_SIBGR_BCLK_T2 0x00000100
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#define TXx927_SIBGR_BCLK_T4 0x00000200
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#define TXx927_SIBGR_BCLK_T6 0x00000300
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#define TXx927_SIBGR_BRD_MASK 0x000000ff
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/*
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* PIO
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*/
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#endif /* __ASM_TXX927_H */
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