forked from luck/tmp_suning_uos_patched
4260415f6a
/tmp/ccJ3ssZW.s: Assembler messages:
/tmp/ccJ3ssZW.s:1952: Error: can't resolve `.text' {.text section} - `.LFB1077'
This is caused because:
.section .data
.section .text
.section .text
.previous
does not return us to the .text section, but the .data section; this
makes use of .previous dangerous if the ordering of previous sections
is not known.
Fix up the other users of .previous; .pushsection and .popsection are
a safer pairing to use than .section and .previous.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
84 lines
1.8 KiB
ArmAsm
84 lines
1.8 KiB
ArmAsm
/*
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* linux/arch/arm/lib/csumpartialcopyuser.S
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*
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* Copyright (C) 1995-1998 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* 27/03/03 Ian Molton Clean up CONFIG_CPU
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*
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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#include <asm/asm-offsets.h>
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.text
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.macro save_regs
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stmfd sp!, {r1, r2, r4 - r8, lr}
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.endm
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.macro load_regs
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ldmfd sp!, {r1, r2, r4 - r8, pc}
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.endm
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.macro load1b, reg1
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ldrusr \reg1, r0, 1
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.endm
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.macro load2b, reg1, reg2
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ldrusr \reg1, r0, 1
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ldrusr \reg2, r0, 1
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.endm
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.macro load1l, reg1
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ldrusr \reg1, r0, 4
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.endm
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.macro load2l, reg1, reg2
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ldrusr \reg1, r0, 4
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ldrusr \reg2, r0, 4
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.endm
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.macro load4l, reg1, reg2, reg3, reg4
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ldrusr \reg1, r0, 4
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ldrusr \reg2, r0, 4
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ldrusr \reg3, r0, 4
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ldrusr \reg4, r0, 4
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.endm
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/*
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* unsigned int
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* csum_partial_copy_from_user(const char *src, char *dst, int len, int sum, int *err_ptr)
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* r0 = src, r1 = dst, r2 = len, r3 = sum, [sp] = *err_ptr
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* Returns : r0 = checksum, [[sp, #0], #0] = 0 or -EFAULT
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*/
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#define FN_ENTRY ENTRY(csum_partial_copy_from_user)
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#define FN_EXIT ENDPROC(csum_partial_copy_from_user)
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#include "csumpartialcopygeneric.S"
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/*
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* FIXME: minor buglet here
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* We don't return the checksum for the data present in the buffer. To do
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* so properly, we would have to add in whatever registers were loaded before
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* the fault, which, with the current asm above is not predictable.
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*/
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.pushsection .fixup,"ax"
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.align 4
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9001: mov r4, #-EFAULT
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ldr r5, [fp, #4] @ *err_ptr
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str r4, [r5]
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ldmia sp, {r1, r2} @ retrieve dst, len
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add r2, r2, r1
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mov r0, #0 @ zero the buffer
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9002: teq r2, r1
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strneb r0, [r1], #1
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bne 9002b
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load_regs
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.popsection
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