kernel_optimize_test/arch/ia64/kernel
Robin Holt 837cd0bdf5 [IA64] 4-level page tables
This patch introduces 4-level page tables to ia64.  I have run
some benchmarks and found nothing interesting.  Performance has
consistently fallen within the noise range.

It also introduces a config option (setting the default to 3
levels).  The config option prevents having 4 level page
tables with 64k base page size.

Signed-off-by: Robin Holt <holt@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
2005-11-11 09:37:29 -08:00
..
cpufreq
acpi-ext.c
acpi.c
asm-offsets.c
brl_emu.c
cyclone.c
efi_stub.S
efi.c [IA64] Replace kcalloc(1, with kzalloc. 2005-11-10 11:28:20 -08:00
entry.h
entry.S
fsys.S
gate-data.S
gate.lds.S
gate.S
head.S
ia64_ksyms.c
init_task.c
iosapic.c
irq_ia64.c
irq_lsapic.c
irq.c
ivt.S [IA64] 4-level page tables 2005-11-11 09:37:29 -08:00
jprobes.S
kprobes.c
machvec.c
Makefile
mca_asm.S
mca_drv_asm.S
mca_drv.c
mca_drv.h
mca.c
minstate.h
module.c
numa.c
pal.S
palinfo.c
patch.c
perfmon_default_smpl.c
perfmon_generic.h
perfmon_itanium.h
perfmon_mckinley.h
perfmon.c
process.c
ptrace.c
sal.c
salinfo.c
semaphore.c
setup.c
sigframe.h
signal.c
smp.c
smpboot.c
sys_ia64.c
time.c
topology.c
traps.c
unaligned.c
uncached.c
unwind_decoder.c
unwind_i.h
unwind.c
vmlinux.lds.S