forked from luck/tmp_suning_uos_patched
368dd5acd1
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
152 lines
3.1 KiB
ArmAsm
152 lines
3.1 KiB
ArmAsm
/* Boot entry point for a compressed MN10300 kernel
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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.section .text
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#define DEBUG
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#include <linux/linkage.h>
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#include <asm/cpu-regs.h>
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#include <asm/cache.h>
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#ifdef CONFIG_SMP
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#include <proc/smp-regs.h>
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#endif
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.globl startup_32
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startup_32:
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#ifdef CONFIG_SMP
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#
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# Secondary CPUs jump directly to the kernel entry point
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#
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# Must save primary CPU's D0-D2 registers as they hold boot parameters
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#
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mov (CPUID), d3
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and CPUID_MASK,d3
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beq startup_primary
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mov CONFIG_KERNEL_TEXT_ADDRESS,a0
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jmp (a0)
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startup_primary:
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#endif /* CONFIG_SMP */
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# first save parameters from bootloader
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mov param_save_area,a0
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mov d0,(a0)
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mov d1,(4,a0)
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mov d2,(8,a0)
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mov sp,a3
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mov decomp_stack+0x2000-4,a0
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mov a0,sp
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# invalidate and enable both of the caches
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mov CHCTR,a0
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clr d0
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movhu d0,(a0) # turn off first
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mov CHCTR_ICINV|CHCTR_DCINV,d0
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movhu d0,(a0)
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setlb
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mov (a0),d0
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btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
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lne
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#ifdef CONFIG_MN10300_CACHE_ENABLED
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#ifdef CONFIG_MN10300_CACHE_WBACK
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0
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#else
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mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0
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#endif /* WBACK */
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movhu d0,(a0) # enable
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#endif /* !ENABLED */
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# clear the BSS area
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mov __bss_start,a0
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mov _end,a1
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clr d0
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bssclear:
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cmp a1,a0
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bge bssclear_end
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movbu d0,(a0)
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inc a0
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bra bssclear
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bssclear_end:
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# decompress the kernel
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call decompress_kernel[],0
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#ifdef CONFIG_MN10300_CACHE_WBACK
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call mn10300_dcache_flush_inv[],0
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#endif
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# disable caches again
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mov CHCTR,a0
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clr d0
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movhu d0,(a0)
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setlb
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mov (a0),d0
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btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy
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lne
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mov param_save_area,a0
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mov (a0),d0
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mov (4,a0),d1
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mov (8,a0),d2
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# jump to the kernel proper entry point
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mov a3,sp
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mov CONFIG_KERNEL_TEXT_ADDRESS,a0
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jmp (a0)
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###############################################################################
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#
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# Cache flush routines
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#
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###############################################################################
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#ifdef CONFIG_MN10300_CACHE_WBACK
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mn10300_dcache_flush_inv:
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movhu (CHCTR),d0
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btst CHCTR_DCEN,d0
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beq mn10300_dcache_flush_inv_end
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mov L1_CACHE_NENTRIES,d1
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clr a1
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mn10300_dcache_flush_inv_loop:
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mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge
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mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge
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mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge
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mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
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add L1_CACHE_BYTES,a1
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add -1,d1
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bne mn10300_dcache_flush_inv_loop
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mn10300_dcache_flush_inv_end:
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ret [],0
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#endif /* CONFIG_MN10300_CACHE_WBACK */
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###############################################################################
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#
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# Data areas
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#
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###############################################################################
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.data
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.align 4
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param_save_area:
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.rept 3
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.word 0
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.endr
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.section .bss
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.align 4
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decomp_stack:
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.space 0x2000
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