forked from luck/tmp_suning_uos_patched
9952f6918d
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms and conditions of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 228 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
241 lines
11 KiB
C
241 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* tegra30_i2s.h - Definitions for Tegra30 I2S driver
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*
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* Copyright (c) 2011,2012, NVIDIA CORPORATION. All rights reserved.
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*/
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#ifndef __TEGRA30_I2S_H__
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#define __TEGRA30_I2S_H__
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#include "tegra_pcm.h"
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/* Register offsets from TEGRA30_I2S*_BASE */
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#define TEGRA30_I2S_CTRL 0x0
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#define TEGRA30_I2S_TIMING 0x4
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#define TEGRA30_I2S_OFFSET 0x08
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#define TEGRA30_I2S_CH_CTRL 0x0c
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#define TEGRA30_I2S_SLOT_CTRL 0x10
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#define TEGRA30_I2S_CIF_RX_CTRL 0x14
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#define TEGRA30_I2S_CIF_TX_CTRL 0x18
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#define TEGRA30_I2S_FLOWCTL 0x1c
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#define TEGRA30_I2S_TX_STEP 0x20
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#define TEGRA30_I2S_FLOW_STATUS 0x24
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#define TEGRA30_I2S_FLOW_TOTAL 0x28
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#define TEGRA30_I2S_FLOW_OVER 0x2c
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#define TEGRA30_I2S_FLOW_UNDER 0x30
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#define TEGRA30_I2S_LCOEF_1_4_0 0x34
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#define TEGRA30_I2S_LCOEF_1_4_1 0x38
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#define TEGRA30_I2S_LCOEF_1_4_2 0x3c
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#define TEGRA30_I2S_LCOEF_1_4_3 0x40
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#define TEGRA30_I2S_LCOEF_1_4_4 0x44
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#define TEGRA30_I2S_LCOEF_1_4_5 0x48
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#define TEGRA30_I2S_LCOEF_2_4_0 0x4c
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#define TEGRA30_I2S_LCOEF_2_4_1 0x50
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#define TEGRA30_I2S_LCOEF_2_4_2 0x54
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/* Fields in TEGRA30_I2S_CTRL */
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#define TEGRA30_I2S_CTRL_XFER_EN_TX (1 << 31)
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#define TEGRA30_I2S_CTRL_XFER_EN_RX (1 << 30)
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#define TEGRA30_I2S_CTRL_CG_EN (1 << 29)
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#define TEGRA30_I2S_CTRL_SOFT_RESET (1 << 28)
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#define TEGRA30_I2S_CTRL_TX_FLOWCTL_EN (1 << 27)
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#define TEGRA30_I2S_CTRL_OBS_SEL_SHIFT 24
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#define TEGRA30_I2S_CTRL_OBS_SEL_MASK (7 << TEGRA30_I2S_CTRL_OBS_SEL_SHIFT)
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#define TEGRA30_I2S_FRAME_FORMAT_LRCK 0
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#define TEGRA30_I2S_FRAME_FORMAT_FSYNC 1
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#define TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT 12
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#define TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK (7 << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK (TEGRA30_I2S_FRAME_FORMAT_LRCK << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC (TEGRA30_I2S_FRAME_FORMAT_FSYNC << TEGRA30_I2S_CTRL_FRAME_FORMAT_SHIFT)
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#define TEGRA30_I2S_CTRL_MASTER_ENABLE (1 << 10)
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#define TEGRA30_I2S_LRCK_LEFT_LOW 0
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#define TEGRA30_I2S_LRCK_RIGHT_LOW 1
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#define TEGRA30_I2S_CTRL_LRCK_SHIFT 9
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#define TEGRA30_I2S_CTRL_LRCK_MASK (1 << TEGRA30_I2S_CTRL_LRCK_SHIFT)
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#define TEGRA30_I2S_CTRL_LRCK_L_LOW (TEGRA30_I2S_LRCK_LEFT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
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#define TEGRA30_I2S_CTRL_LRCK_R_LOW (TEGRA30_I2S_LRCK_RIGHT_LOW << TEGRA30_I2S_CTRL_LRCK_SHIFT)
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#define TEGRA30_I2S_CTRL_LPBK_ENABLE (1 << 8)
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#define TEGRA30_I2S_BIT_CODE_LINEAR 0
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#define TEGRA30_I2S_BIT_CODE_ULAW 1
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#define TEGRA30_I2S_BIT_CODE_ALAW 2
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#define TEGRA30_I2S_CTRL_BIT_CODE_SHIFT 4
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#define TEGRA30_I2S_CTRL_BIT_CODE_MASK (3 << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_CODE_LINEAR (TEGRA30_I2S_BIT_CODE_LINEAR << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_CODE_ULAW (TEGRA30_I2S_BIT_CODE_ULAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_CODE_ALAW (TEGRA30_I2S_BIT_CODE_ALAW << TEGRA30_I2S_CTRL_BIT_CODE_SHIFT)
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#define TEGRA30_I2S_BITS_8 1
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#define TEGRA30_I2S_BITS_12 2
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#define TEGRA30_I2S_BITS_16 3
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#define TEGRA30_I2S_BITS_20 4
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#define TEGRA30_I2S_BITS_24 5
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#define TEGRA30_I2S_BITS_28 6
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#define TEGRA30_I2S_BITS_32 7
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/* Sample container size; see {RX,TX}_MASK field in CH_CTRL below */
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#define TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT 0
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#define TEGRA30_I2S_CTRL_BIT_SIZE_MASK (7 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_8 (TEGRA30_I2S_BITS_8 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_12 (TEGRA30_I2S_BITS_12 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_16 (TEGRA30_I2S_BITS_16 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_20 (TEGRA30_I2S_BITS_20 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_24 (TEGRA30_I2S_BITS_24 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_28 (TEGRA30_I2S_BITS_28 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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#define TEGRA30_I2S_CTRL_BIT_SIZE_32 (TEGRA30_I2S_BITS_32 << TEGRA30_I2S_CTRL_BIT_SIZE_SHIFT)
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/* Fields in TEGRA30_I2S_TIMING */
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#define TEGRA30_I2S_TIMING_NON_SYM_ENABLE (1 << 12)
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#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT 0
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#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US 0x7ff
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#define TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK (TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT)
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/* Fields in TEGRA30_I2S_OFFSET */
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#define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT 16
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#define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US 0x7ff
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#define TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT)
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#define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT 0
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#define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US 0x7ff
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#define TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK (TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_MASK_US << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT)
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/* Fields in TEGRA30_I2S_CH_CTRL */
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/* (FSYNC width - 1) in bit clocks */
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#define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT 24
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#define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US 0xff
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#define TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK (TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_MASK_US << TEGRA30_I2S_CH_CTRL_FSYNC_WIDTH_SHIFT)
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#define TEGRA30_I2S_HIGHZ_NO 0
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#define TEGRA30_I2S_HIGHZ_YES 1
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#define TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK 2
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#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT 12
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#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_MASK (3 << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_NO (TEGRA30_I2S_HIGHZ_NO << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_YES (TEGRA30_I2S_HIGHZ_YES << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_ON_HALF_BIT_CLK (TEGRA30_I2S_HIGHZ_ON_HALF_BIT_CLK << TEGRA30_I2S_CH_CTRL_HIGHZ_CTRL_SHIFT)
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#define TEGRA30_I2S_MSB_FIRST 0
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#define TEGRA30_I2S_LSB_FIRST 1
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#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT 10
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#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_RX_BIT_ORDER_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT 9
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#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MASK (1 << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_MSB_FIRST (TEGRA30_I2S_MSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_LSB_FIRST (TEGRA30_I2S_LSB_FIRST << TEGRA30_I2S_CH_CTRL_TX_BIT_ORDER_SHIFT)
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#define TEGRA30_I2S_POS_EDGE 0
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#define TEGRA30_I2S_NEG_EDGE 1
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#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT 8
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#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK (1 << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_POS_EDGE (TEGRA30_I2S_POS_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE (TEGRA30_I2S_NEG_EDGE << TEGRA30_I2S_CH_CTRL_EGDE_CTRL_SHIFT)
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/* Sample size is # bits from BIT_SIZE minus this field */
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#define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT 4
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#define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US 7
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#define TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_RX_MASK_BITS_SHIFT)
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#define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT 0
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#define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US 7
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#define TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK (TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_MASK_US << TEGRA30_I2S_CH_CTRL_TX_MASK_BITS_SHIFT)
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/* Fields in TEGRA30_I2S_SLOT_CTRL */
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/* Number of slots in frame, minus 1 */
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#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT 16
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#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US 7
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#define TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK (TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_MASK_US << TEGRA30_I2S_SLOT_CTRL_TOTAL_SLOTS_SHIFT)
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/* TDM mode slot enable bitmask */
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#define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT 8
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#define TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_RX_SLOT_ENABLES_SHIFT)
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#define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT 0
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#define TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_MASK (0xff << TEGRA30_I2S_SLOT_CTRL_TX_SLOT_ENABLES_SHIFT)
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/* Fields in TEGRA30_I2S_CIF_RX_CTRL */
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/* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
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/* Fields in TEGRA30_I2S_CIF_TX_CTRL */
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/* Uses field from TEGRA30_AUDIOCIF_CTRL_* in tegra30_ahub.h */
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/* Fields in TEGRA30_I2S_FLOWCTL */
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#define TEGRA30_I2S_FILTER_LINEAR 0
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#define TEGRA30_I2S_FILTER_QUAD 1
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#define TEGRA30_I2S_FLOWCTL_FILTER_SHIFT 31
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#define TEGRA30_I2S_FLOWCTL_FILTER_MASK (1 << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
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#define TEGRA30_I2S_FLOWCTL_FILTER_LINEAR (TEGRA30_I2S_FILTER_LINEAR << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
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#define TEGRA30_I2S_FLOWCTL_FILTER_QUAD (TEGRA30_I2S_FILTER_QUAD << TEGRA30_I2S_FLOWCTL_FILTER_SHIFT)
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/* Fields in TEGRA30_I2S_TX_STEP */
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#define TEGRA30_I2S_TX_STEP_SHIFT 0
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#define TEGRA30_I2S_TX_STEP_MASK_US 0xffff
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#define TEGRA30_I2S_TX_STEP_MASK (TEGRA30_I2S_TX_STEP_MASK_US << TEGRA30_I2S_TX_STEP_SHIFT)
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/* Fields in TEGRA30_I2S_FLOW_STATUS */
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#define TEGRA30_I2S_FLOW_STATUS_UNDERFLOW (1 << 31)
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#define TEGRA30_I2S_FLOW_STATUS_OVERFLOW (1 << 30)
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#define TEGRA30_I2S_FLOW_STATUS_MONITOR_INT_EN (1 << 4)
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#define TEGRA30_I2S_FLOW_STATUS_COUNTER_CLR (1 << 3)
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#define TEGRA30_I2S_FLOW_STATUS_MONITOR_CLR (1 << 2)
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#define TEGRA30_I2S_FLOW_STATUS_COUNTER_EN (1 << 1)
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#define TEGRA30_I2S_FLOW_STATUS_MONITOR_EN (1 << 0)
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/*
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* There are no fields in TEGRA30_I2S_FLOW_TOTAL, TEGRA30_I2S_FLOW_OVER,
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* TEGRA30_I2S_FLOW_UNDER; they are counters taking the whole register.
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*/
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/* Fields in TEGRA30_I2S_LCOEF_* */
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#define TEGRA30_I2S_LCOEF_COEF_SHIFT 0
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#define TEGRA30_I2S_LCOEF_COEF_MASK_US 0xffff
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#define TEGRA30_I2S_LCOEF_COEF_MASK (TEGRA30_I2S_LCOEF_COEF_MASK_US << TEGRA30_I2S_LCOEF_COEF_SHIFT)
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struct tegra30_i2s_soc_data {
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void (*set_audio_cif)(struct regmap *regmap,
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unsigned int reg,
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struct tegra30_ahub_cif_conf *conf);
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};
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struct tegra30_i2s {
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const struct tegra30_i2s_soc_data *soc_data;
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struct snd_soc_dai_driver dai;
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int cif_id;
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struct clk *clk_i2s;
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enum tegra30_ahub_txcif capture_i2s_cif;
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enum tegra30_ahub_rxcif capture_fifo_cif;
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char capture_dma_chan[8];
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struct snd_dmaengine_dai_dma_data capture_dma_data;
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enum tegra30_ahub_rxcif playback_i2s_cif;
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enum tegra30_ahub_txcif playback_fifo_cif;
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char playback_dma_chan[8];
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struct snd_dmaengine_dai_dma_data playback_dma_data;
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struct regmap *regmap;
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struct snd_dmaengine_pcm_config dma_config;
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};
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#endif
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