forked from luck/tmp_suning_uos_patched
af75655c06
picoXcell is a family of femtocell devices with an ARM application processor and picoArray DSP processor array. This patch adds support for picoXcell boards to be booted using the device tree registering the VIC's, UART's and timers. v3: - fixup vic compatible string in binding v2: - cleanup empty mach headers - convert to of_platform_populate() - simplify uncompress.h - split vic node into 2 devices - add missing __initconst attributes Signed-off-by: Jamie Iles <jamie@jamieiles.com>
133 lines
3.2 KiB
C
133 lines
3.2 KiB
C
/*
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* Copyright (c) 2011 Picochip Ltd., Jamie Iles
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* All enquiries to support@picochip.com
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*/
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#include <linux/dw_apb_timer.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/sched.h>
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#include <asm/mach/time.h>
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#include <asm/sched_clock.h>
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#include "common.h"
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static void timer_get_base_and_rate(struct device_node *np,
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void __iomem **base, u32 *rate)
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{
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*base = of_iomap(np, 0);
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if (!*base)
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panic("Unable to map regs for %s", np->name);
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if (of_property_read_u32(np, "clock-freq", rate))
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panic("No clock-freq property for %s", np->name);
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}
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static void picoxcell_add_clockevent(struct device_node *event_timer)
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{
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void __iomem *iobase;
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struct dw_apb_clock_event_device *ced;
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u32 irq, rate;
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irq = irq_of_parse_and_map(event_timer, 0);
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if (irq == NO_IRQ)
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panic("No IRQ for clock event timer");
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timer_get_base_and_rate(event_timer, &iobase, &rate);
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ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq,
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rate);
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if (!ced)
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panic("Unable to initialise clockevent device");
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dw_apb_clockevent_register(ced);
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}
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static void picoxcell_add_clocksource(struct device_node *source_timer)
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{
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void __iomem *iobase;
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struct dw_apb_clocksource *cs;
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u32 rate;
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timer_get_base_and_rate(source_timer, &iobase, &rate);
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cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate);
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if (!cs)
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panic("Unable to initialise clocksource device");
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dw_apb_clocksource_start(cs);
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dw_apb_clocksource_register(cs);
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}
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static DEFINE_CLOCK_DATA(cd);
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static void __iomem *sched_io_base;
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unsigned long long notrace sched_clock(void)
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{
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cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
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return cyc_to_sched_clock(&cd, cyc, (u32)~0);
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}
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static void notrace picoxcell_update_sched_clock(void)
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{
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cycle_t cyc = sched_io_base ? __raw_readl(sched_io_base) : 0;
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update_sched_clock(&cd, cyc, (u32)~0);
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}
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static const struct of_device_id picoxcell_rtc_ids[] __initconst = {
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{ .compatible = "picochip,pc3x2-rtc" },
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{ /* Sentinel */ },
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};
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static void picoxcell_init_sched_clock(void)
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{
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struct device_node *sched_timer;
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u32 rate;
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sched_timer = of_find_matching_node(NULL, picoxcell_rtc_ids);
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if (!sched_timer)
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panic("No RTC for sched clock to use");
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timer_get_base_and_rate(sched_timer, &sched_io_base, &rate);
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of_node_put(sched_timer);
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init_sched_clock(&cd, picoxcell_update_sched_clock, 32, rate);
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}
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static const struct of_device_id picoxcell_timer_ids[] __initconst = {
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{ .compatible = "picochip,pc3x2-timer" },
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{},
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};
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static void __init picoxcell_timer_init(void)
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{
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struct device_node *event_timer, *source_timer;
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event_timer = of_find_matching_node(NULL, picoxcell_timer_ids);
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if (!event_timer)
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panic("No timer for clockevent");
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picoxcell_add_clockevent(event_timer);
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source_timer = of_find_matching_node(event_timer, picoxcell_timer_ids);
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if (!source_timer)
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panic("No timer for clocksource");
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picoxcell_add_clocksource(source_timer);
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of_node_put(source_timer);
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picoxcell_init_sched_clock();
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}
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struct sys_timer picoxcell_timer = {
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.init = picoxcell_timer_init,
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};
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