forked from luck/tmp_suning_uos_patched
d5fdafd38c
Currently tegra_pcie_init is effectively called as subsys_initcall. With multiplatform kernel this may cause hangs on boards that don't intend to support Tegra2 PCI-e. Ensure that TrimSlice board code initializes PCI-e only when actually running on the TrimSlice. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Colin Cross <ccross@android.com>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* arch/arm/mach-tegra/board-trimslice.c
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*
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* Copyright (C) 2011 CompuLab, Ltd.
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* Author: Mike Rapoport <mike@compulab.co.il>
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*
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* Based on board-harmony.c
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/setup.h>
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#include <mach/iomap.h>
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#include "board.h"
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#include "clock.h"
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#include "board-trimslice.h"
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static struct plat_serial8250_port debug_uart_platform_data[] = {
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{
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.membase = IO_ADDRESS(TEGRA_UARTA_BASE),
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.mapbase = TEGRA_UARTA_BASE,
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.irq = INT_UARTA,
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.flags = UPF_BOOT_AUTOCONF,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = 216000000,
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}, {
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.flags = 0
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}
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};
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static struct platform_device debug_uart = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = debug_uart_platform_data,
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},
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};
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static struct platform_device *trimslice_devices[] __initdata = {
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&debug_uart,
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};
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static void __init tegra_trimslice_fixup(struct machine_desc *desc,
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struct tag *tags, char **cmdline, struct meminfo *mi)
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{
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mi->nr_banks = 2;
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mi->bank[0].start = PHYS_OFFSET;
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mi->bank[0].size = 448 * SZ_1M;
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mi->bank[1].start = SZ_512M;
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mi->bank[1].size = SZ_512M;
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}
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static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
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/* name parent rate enabled */
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{ "uarta", "pll_p", 216000000, true },
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{ NULL, NULL, 0, 0},
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};
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static int __init tegra_trimslice_pci_init(void)
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{
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if (!machine_is_trimslice())
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return 0;
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return tegra_pcie_init(true, true);
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}
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subsys_initcall(tegra_trimslice_pci_init);
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static void __init tegra_trimslice_init(void)
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{
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tegra_clk_init_from_table(trimslice_clk_init_table);
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trimslice_pinmux_init();
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platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
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}
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MACHINE_START(TRIMSLICE, "trimslice")
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.boot_params = 0x00000100,
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.fixup = tegra_trimslice_fixup,
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.map_io = tegra_map_common_io,
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.init_early = tegra_init_early,
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.init_irq = tegra_init_irq,
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.timer = &tegra_timer,
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.init_machine = tegra_trimslice_init,
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MACHINE_END
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