forked from luck/tmp_suning_uos_patched
77c5f5d2f2
Register GHES at EDAC MC core, in order to avoid other drivers to also handle errors and mangle with error data. The edac core will warrant that just one driver will be used, so the first one to register (BIOS first) will be the one that will be reporting the hardware errors. For now, the EDAC driver does nothing but to register at the EDAC core, preventing the hardware-driven mechanism to interfere with GHES. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
115 lines
2.6 KiB
C
115 lines
2.6 KiB
C
/*
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* GHES/EDAC Linux driver
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*
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* This file may be distributed under the terms of the GNU General Public
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* License version 2.
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*
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* Copyright (c) 2013 by Mauro Carvalho Chehab <mchehab@redhat.com>
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*
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* Red Hat Inc. http://www.redhat.com
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*/
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#include <acpi/ghes.h>
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#include <linux/edac.h>
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#include "edac_core.h"
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#define GHES_PFX "ghes_edac: "
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#define GHES_EDAC_REVISION " Ver: 1.0.0"
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struct ghes_edac_pvt {
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struct list_head list;
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struct ghes *ghes;
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struct mem_ctl_info *mci;
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};
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static LIST_HEAD(ghes_reglist);
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static DEFINE_MUTEX(ghes_edac_lock);
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static int ghes_edac_mc_num;
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void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
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struct cper_sec_mem_err *mem_err)
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{
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}
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EXPORT_SYMBOL_GPL(ghes_edac_report_mem_error);
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int ghes_edac_register(struct ghes *ghes, struct device *dev)
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{
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int rc;
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struct mem_ctl_info *mci;
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struct edac_mc_layer layers[1];
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struct csrow_info *csrow;
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struct dimm_info *dimm;
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struct ghes_edac_pvt *pvt;
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layers[0].type = EDAC_MC_LAYER_ALL_MEM;
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layers[0].size = 1;
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layers[0].is_virt_csrow = true;
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/*
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* We need to serialize edac_mc_alloc() and edac_mc_add_mc(),
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* to avoid duplicated memory controller numbers
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*/
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mutex_lock(&ghes_edac_lock);
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mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,
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sizeof(*pvt));
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if (!mci) {
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pr_info(GHES_PFX "Can't allocate memory for EDAC data\n");
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mutex_unlock(&ghes_edac_lock);
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return -ENOMEM;
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}
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pvt = mci->pvt_info;
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memset(pvt, 0, sizeof(*pvt));
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list_add_tail(&pvt->list, &ghes_reglist);
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pvt->ghes = ghes;
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pvt->mci = mci;
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mci->pdev = dev;
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mci->mtype_cap = MEM_FLAG_EMPTY;
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mci->edac_ctl_cap = EDAC_FLAG_NONE;
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mci->edac_cap = EDAC_FLAG_NONE;
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mci->mod_name = "ghes_edac.c";
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mci->mod_ver = GHES_EDAC_REVISION;
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mci->ctl_name = "ghes_edac";
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mci->dev_name = "ghes";
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csrow = mci->csrows[0];
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dimm = csrow->channels[0]->dimm;
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/* FIXME: FAKE DATA */
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dimm->nr_pages = 1000;
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dimm->grain = 128;
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dimm->mtype = MEM_UNKNOWN;
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dimm->dtype = DEV_UNKNOWN;
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dimm->edac_mode = EDAC_SECDED;
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rc = edac_mc_add_mc(mci);
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if (rc < 0) {
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pr_info(GHES_PFX "Can't register at EDAC core\n");
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edac_mc_free(mci);
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mutex_unlock(&ghes_edac_lock);
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return -ENODEV;
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}
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ghes_edac_mc_num++;
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mutex_unlock(&ghes_edac_lock);
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return 0;
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}
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EXPORT_SYMBOL_GPL(ghes_edac_register);
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void ghes_edac_unregister(struct ghes *ghes)
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{
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struct mem_ctl_info *mci;
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struct ghes_edac_pvt *pvt;
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list_for_each_entry(pvt, &ghes_reglist, list) {
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if (ghes == pvt->ghes) {
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mci = pvt->mci;
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edac_mc_del_mc(mci->pdev);
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edac_mc_free(mci);
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list_del(&pvt->list);
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}
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}
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}
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EXPORT_SYMBOL_GPL(ghes_edac_unregister);
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