forked from luck/tmp_suning_uos_patched
76fbfc318d
mm_isBranchInstr() did reside in the math emu code even though it logically
is separate and also is used outside the math emu code. In addition GCC 4.9.0
leaves the following unnnecessarily bloated function body for a non-microMIPS
configuration:
<mm_isBranchInstr>:
105c: afa50004 sw a1,4(sp)
1060: afa60008 sw a2,8(sp)
1064: afa7000c sw a3,12(sp)
1068: 03e00008 jr ra
106c: 00001021 move v0,zero
which stores arguments that are never going to be used on the stack frame.
Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr()
into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function
which only invokes __mm_isBranchInstr() on microMIPS configurations.
This shaves off 112 bytes off the kernel and improves code flow a bit.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
104 lines
2.4 KiB
C
104 lines
2.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
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*/
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#ifndef _ASM_BRANCH_H
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#define _ASM_BRANCH_H
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#include <asm/cpu-features.h>
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#include <asm/mipsregs.h>
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#include <asm/ptrace.h>
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#include <asm/inst.h>
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extern int __isa_exception_epc(struct pt_regs *regs);
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extern int __compute_return_epc(struct pt_regs *regs);
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extern int __compute_return_epc_for_insn(struct pt_regs *regs,
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union mips_instruction insn);
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extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
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extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
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/*
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* microMIPS bitfields
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*/
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#define MM_POOL32A_MINOR_MASK 0x3f
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#define MM_POOL32A_MINOR_SHIFT 0x6
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#define MM_MIPS32_COND_FC 0x30
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extern int __mm_isBranchInstr(struct pt_regs *regs,
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struct mm_decoded_insn dec_insn, unsigned long *contpc);
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static inline int mm_isBranchInstr(struct pt_regs *regs,
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struct mm_decoded_insn dec_insn, unsigned long *contpc)
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{
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if (!cpu_has_mmips)
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return 0;
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return __mm_isBranchInstr(regs, dec_insn, contpc);
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}
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static inline int delay_slot(struct pt_regs *regs)
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{
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return regs->cp0_cause & CAUSEF_BD;
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}
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static inline void clear_delay_slot(struct pt_regs *regs)
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{
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regs->cp0_cause &= ~CAUSEF_BD;
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}
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static inline void set_delay_slot(struct pt_regs *regs)
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{
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regs->cp0_cause |= CAUSEF_BD;
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}
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static inline unsigned long exception_epc(struct pt_regs *regs)
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{
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if (likely(!delay_slot(regs)))
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return regs->cp0_epc;
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if (get_isa16_mode(regs->cp0_epc))
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return __isa_exception_epc(regs);
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return regs->cp0_epc + 4;
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}
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#define BRANCH_LIKELY_TAKEN 0x0001
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static inline int compute_return_epc(struct pt_regs *regs)
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{
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if (get_isa16_mode(regs->cp0_epc)) {
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if (cpu_has_mmips)
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return __microMIPS_compute_return_epc(regs);
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if (cpu_has_mips16)
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return __MIPS16e_compute_return_epc(regs);
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return regs->cp0_epc;
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}
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if (!delay_slot(regs)) {
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regs->cp0_epc += 4;
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return 0;
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}
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return __compute_return_epc(regs);
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}
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static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
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union mips16e_instruction *inst)
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{
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if (likely(!delay_slot(regs))) {
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if (inst->ri.opcode == MIPS16e_extend_op) {
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regs->cp0_epc += 4;
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return 0;
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}
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regs->cp0_epc += 2;
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return 0;
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}
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return __MIPS16e_compute_return_epc(regs);
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}
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#endif /* _ASM_BRANCH_H */
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