forked from luck/tmp_suning_uos_patched
eb7bd9c461
The handling of updating the [DI]MEM_CONTROL MMRs does not follow proper sync procedures as laid out in the Blackfin programming manual. So rather than audit/fix every call location, create helper functions that do the right things in order to safely update these MMRs. Then convert all call sites to use these new helper functions. While we're fixing the code, drop the workaround for anomaly 05000125 as that anomaly applies to old versions of silicon that we do not support. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
294 lines
7.1 KiB
C
294 lines
7.1 KiB
C
/*
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* File: arch/blackfin/mach-common/pm.c
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* Based on: arm/mach-omap/pm.c
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* Author: Cliff Brake <cbrake@accelent.com> Copyright (c) 2001
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*
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* Created: 2001
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* Description: Blackfin power management
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*
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* Modified: Nicolas Pitre - PXA250 support
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* Copyright (c) 2002 Monta Vista Software, Inc.
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* David Singleton - OMAP1510
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* Copyright (c) 2002 Monta Vista Software, Inc.
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* Dirk Behme <dirk.behme@de.bosch.com> - OMAP1510/1610
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* Copyright 2004
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* Copyright 2004-2008 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/suspend.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <asm/cplb.h>
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#include <asm/gpio.h>
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#include <asm/dma.h>
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#include <asm/dpmc.h>
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#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_H
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#define WAKEUP_TYPE PM_WAKE_HIGH
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#endif
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#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_L
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#define WAKEUP_TYPE PM_WAKE_LOW
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#endif
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#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_F
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#define WAKEUP_TYPE PM_WAKE_FALLING
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#endif
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#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_R
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#define WAKEUP_TYPE PM_WAKE_RISING
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#endif
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#ifdef CONFIG_PM_WAKEUP_GPIO_POLAR_EDGE_B
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#define WAKEUP_TYPE PM_WAKE_BOTH_EDGES
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#endif
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void bfin_pm_suspend_standby_enter(void)
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{
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unsigned long flags;
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#ifdef CONFIG_PM_WAKEUP_BY_GPIO
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gpio_pm_wakeup_request(CONFIG_PM_WAKEUP_GPIO_NUMBER, WAKEUP_TYPE);
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#endif
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local_irq_save_hw(flags);
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bfin_pm_standby_setup();
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#ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
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sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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#else
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sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
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#endif
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bfin_pm_standby_restore();
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#ifdef SIC_IWR0
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bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
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# ifdef SIC_IWR1
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/* BF52x system reset does not properly reset SIC_IWR1 which
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* will screw up the bootrom as it relies on MDMA0/1 waking it
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* up from IDLE instructions. See this report for more info:
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* http://blackfin.uclinux.org/gf/tracker/4323
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*/
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if (ANOMALY_05000435)
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bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
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else
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bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
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# endif
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# ifdef SIC_IWR2
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bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
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# endif
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#else
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bfin_write_SIC_IWR(IWR_DISABLE_ALL);
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#endif
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local_irq_restore_hw(flags);
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}
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int bf53x_suspend_l1_mem(unsigned char *memptr)
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{
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dma_memcpy(memptr, (const void *) L1_CODE_START, L1_CODE_LENGTH);
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dma_memcpy(memptr + L1_CODE_LENGTH, (const void *) L1_DATA_A_START,
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L1_DATA_A_LENGTH);
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dma_memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
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(const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
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memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
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L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
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L1_SCRATCH_LENGTH);
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return 0;
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}
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int bf53x_resume_l1_mem(unsigned char *memptr)
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{
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dma_memcpy((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
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dma_memcpy((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
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L1_DATA_A_LENGTH);
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dma_memcpy((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
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L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
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memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
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L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
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return 0;
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}
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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static void flushinv_all_dcache(void)
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{
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u32 way, bank, subbank, set;
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u32 status, addr;
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u32 dmem_ctl = bfin_read_DMEM_CONTROL();
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for (bank = 0; bank < 2; ++bank) {
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if (!(dmem_ctl & (1 << (DMC1_P - bank))))
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continue;
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for (way = 0; way < 2; ++way)
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for (subbank = 0; subbank < 4; ++subbank)
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for (set = 0; set < 64; ++set) {
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bfin_write_DTEST_COMMAND(
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way << 26 |
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bank << 23 |
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subbank << 16 |
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set << 5
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);
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CSYNC();
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status = bfin_read_DTEST_DATA0();
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/* only worry about valid/dirty entries */
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if ((status & 0x3) != 0x3)
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continue;
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/* construct the address using the tag */
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addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
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/* flush it */
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__asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
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}
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}
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}
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#endif
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int bfin_pm_suspend_mem_enter(void)
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{
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unsigned long flags;
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int wakeup, ret;
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unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
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+ L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
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GFP_KERNEL);
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if (memptr == NULL) {
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panic("bf53x_suspend_l1_mem malloc failed");
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return -ENOMEM;
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}
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wakeup = bfin_read_VR_CTL() & ~FREQ;
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wakeup |= SCKELOW;
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#ifdef CONFIG_PM_BFIN_WAKE_PH6
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wakeup |= PHYWE;
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#endif
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#ifdef CONFIG_PM_BFIN_WAKE_GP
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wakeup |= GPWE;
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#endif
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local_irq_save_hw(flags);
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ret = blackfin_dma_suspend();
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if (ret) {
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local_irq_restore_hw(flags);
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kfree(memptr);
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return ret;
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}
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bfin_gpio_pm_hibernate_suspend();
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#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
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flushinv_all_dcache();
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#endif
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_disable_dcplb();
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_disable_icplb();
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bf53x_suspend_l1_mem(memptr);
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do_hibernate(wakeup | vr_wakeup); /* Goodbye */
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bf53x_resume_l1_mem(memptr);
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_enable_icplb();
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_enable_dcplb();
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bfin_gpio_pm_hibernate_restore();
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blackfin_dma_resume();
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local_irq_restore_hw(flags);
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kfree(memptr);
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return 0;
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}
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/*
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* bfin_pm_valid - Tell the PM core that we only support the standby sleep
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* state
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* @state: suspend state we're checking.
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*
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*/
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static int bfin_pm_valid(suspend_state_t state)
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{
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return (state == PM_SUSPEND_STANDBY
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#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
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/*
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* On BF533/2/1:
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* If we enter Hibernate the SCKE Pin is driven Low,
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* so that the SDRAM enters Self Refresh Mode.
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* However when the reset sequence that follows hibernate
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* state is executed, SCKE is driven High, taking the
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* SDRAM out of Self Refresh.
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*
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* If you reconfigure and access the SDRAM "very quickly",
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* you are likely to avoid errors, otherwise the SDRAM
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* start losing its contents.
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* An external HW workaround is possible using logic gates.
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*/
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|| state == PM_SUSPEND_MEM
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#endif
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);
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}
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/*
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* bfin_pm_enter - Actually enter a sleep state.
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* @state: State we're entering.
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*
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*/
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static int bfin_pm_enter(suspend_state_t state)
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{
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switch (state) {
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case PM_SUSPEND_STANDBY:
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bfin_pm_suspend_standby_enter();
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break;
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case PM_SUSPEND_MEM:
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bfin_pm_suspend_mem_enter();
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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struct platform_suspend_ops bfin_pm_ops = {
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.enter = bfin_pm_enter,
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.valid = bfin_pm_valid,
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};
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static int __init bfin_pm_init(void)
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{
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suspend_set_ops(&bfin_pm_ops);
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return 0;
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}
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__initcall(bfin_pm_init);
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