forked from luck/tmp_suning_uos_patched
087d7e56de
found a system where x2apic reports an MSI-X irq initialization failure: [ 302.859446] igbvf 0000:81:10.4: enabling device (0000 -> 0002) [ 302.874369] igbvf 0000:81:10.4: using 64bit DMA mask [ 302.879023] igbvf 0000:81:10.4: using 64bit consistent DMA mask [ 302.894386] igbvf 0000:81:10.4: enabling bus mastering [ 302.898171] igbvf 0000:81:10.4: setting latency timer to 64 [ 302.914050] reserve_memtype added 0xefb08000-0xefb0c000, track uncached-minus, req uncached-minus, ret uncached-minus [ 302.933839] reserve_memtype added 0xefb28000-0xefb29000, track uncached-minus, req uncached-minus, ret uncached-minus [ 302.940367] alloc irq_desc for 265 on node 4 [ 302.956874] alloc kstat_irqs on node 4 [ 302.959452] alloc irq_2_iommu on node 0 [ 302.974328] igbvf 0000:81:10.4: irq 265 for MSI/MSI-X [ 302.977778] alloc irq_desc for 266 on node 4 [ 302.980347] alloc kstat_irqs on node 4 [ 302.995312] free_memtype request 0xefb28000-0xefb29000 [ 302.998816] igbvf 0000:81:10.4: Failed to initialize MSI-X interrupts. ... it turns out that when trying to enable MSI-X, __assign_irq_vector(new, cfg_new, apic->target_cpus()) can not get vector because for x2apic target-cpus returns cpumask_of(0) Update that to online_mask like xapic. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> LKML-Reference: <4A785AFF.3050902@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
237 lines
5.3 KiB
C
237 lines
5.3 KiB
C
#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/dmar.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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int x2apic_phys;
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static int set_x2apic_phys_mode(char *arg)
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{
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x2apic_phys = 1;
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return 0;
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}
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early_param("x2apic_phys", set_x2apic_phys_mode);
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static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (x2apic_phys)
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return x2apic_enabled();
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else
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return 0;
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}
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/*
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* need to use more than cpu 0, because we need more vectors when
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* MSI-X are used.
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*/
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static const struct cpumask *x2apic_target_cpus(void)
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{
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return cpu_online_mask;
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}
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static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
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{
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cpumask_clear(retmask);
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cpumask_set_cpu(cpu, retmask);
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}
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static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
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unsigned int dest)
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{
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unsigned long cfg;
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* send the IPI.
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*/
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native_x2apic_icr_write(cfg, apicid);
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}
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static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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unsigned long query_cpu;
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unsigned long flags;
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x2apic_wrmsr_fence();
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask) {
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__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
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vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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static void
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x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
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{
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unsigned long this_cpu = smp_processor_id();
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unsigned long query_cpu;
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unsigned long flags;
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x2apic_wrmsr_fence();
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local_irq_save(flags);
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for_each_cpu(query_cpu, mask) {
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if (query_cpu != this_cpu)
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__x2apic_send_IPI_dest(
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per_cpu(x86_cpu_to_apicid, query_cpu),
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vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_allbutself(int vector)
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{
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unsigned long this_cpu = smp_processor_id();
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unsigned long query_cpu;
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unsigned long flags;
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x2apic_wrmsr_fence();
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local_irq_save(flags);
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for_each_online_cpu(query_cpu) {
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if (query_cpu == this_cpu)
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continue;
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__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
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vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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static void x2apic_send_IPI_all(int vector)
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{
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x2apic_send_IPI_mask(cpu_online_mask, vector);
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}
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static int x2apic_apic_id_registered(void)
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{
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return 1;
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}
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static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
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{
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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int cpu = cpumask_first(cpumask);
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if ((unsigned)cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu);
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else
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return BAD_APICID;
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}
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static unsigned int
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x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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const struct cpumask *andmask)
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{
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int cpu;
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/*
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* We're using fixed IRQ delivery, can only return one phys APIC ID.
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* May as well be the first.
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*/
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for_each_cpu_and(cpu, cpumask, andmask) {
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if (cpumask_test_cpu(cpu, cpu_online_mask))
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break;
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}
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if (cpu < nr_cpu_ids)
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return per_cpu(x86_cpu_to_apicid, cpu);
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return BAD_APICID;
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}
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static unsigned int x2apic_phys_get_apic_id(unsigned long x)
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{
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return x;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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return id;
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}
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static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
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{
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return initial_apicid >> index_msb;
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}
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static void x2apic_send_IPI_self(int vector)
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{
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apic_write(APIC_SELF_IPI, vector);
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}
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static void init_x2apic_ldr(void)
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{
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}
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struct apic apic_x2apic_phys = {
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.name = "physical x2apic",
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.probe = NULL,
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.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
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.apic_id_registered = x2apic_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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.irq_dest_mode = 0, /* physical */
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.target_cpus = x2apic_target_cpus,
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.disable_esr = 0,
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.dest_logical = 0,
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.check_apicid_used = NULL,
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.check_apicid_present = NULL,
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.vector_allocation_domain = x2apic_vector_allocation_domain,
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.init_apic_ldr = init_x2apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.multi_timer_check = NULL,
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.apicid_to_node = NULL,
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.cpu_to_logical_apicid = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = NULL,
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = x2apic_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = x2apic_phys_get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = 0xFFFFFFFFu,
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.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
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.cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and,
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.send_IPI_mask = x2apic_send_IPI_mask,
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.send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself,
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.send_IPI_allbutself = x2apic_send_IPI_allbutself,
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.send_IPI_all = x2apic_send_IPI_all,
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.send_IPI_self = x2apic_send_IPI_self,
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.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
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.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
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.wait_for_init_deassert = NULL,
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.smp_callin_clear_local_apic = NULL,
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.inquire_remote_apic = NULL,
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.read = native_apic_msr_read,
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.write = native_apic_msr_write,
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.icr_read = native_x2apic_icr_read,
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.icr_write = native_x2apic_icr_write,
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.wait_icr_idle = native_x2apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
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};
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