Kevin Cernekee d74b0172e4 MIPS: BMIPS: Add special cache handling in c-r4k.c ... BMIPS435x and BMIPS438x have a single shared L1 D$ and load/store unit, so it isn't necessary to raise IPIs to keep both CPUs coherent. BMIPS5000 has VIPT L1 caches that handle aliases in hardware, and its I$ fills from D$. But a special sequence with 2 SYNCs and 32 NOPs is needed to ensure coherency. Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: mbizon@freebox.fr Cc: jogo@openwrt.org Cc: jfraser@broadcom.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8165/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2014-11-24 07:45:12 +01:00
..
c-octeon.c
c-r3k.c
c-r4k.c
c-tx39.c
cache.c
cerr-sb1.c
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c
extable.c
fault.c
gup.c
highmem.c
hugetlbpage.c
init.c
ioremap.c
Makefile
mmap.c
page-funcs.S
page.c
pgtable-32.c
pgtable-64.c
sc-ip22.c
sc-mips.c
sc-r5k.c
sc-rm7k.c
tlb-funcs.S
tlb-r3k.c
tlb-r4k.c
tlb-r8k.c
tlbex-fault.S
tlbex.c
uasm-micromips.c
uasm-mips.c
uasm.c