forked from luck/tmp_suning_uos_patched
8673c1d7e8
The ARM RealView PB11MPCore reference design has some special bits in a system controller register to set up the GIC in one of three modes: legacy, new with DCC, new without DCC. The register is also used to enable FIQ. Since the platform will not boot unless this register is set up to "new with DCC" mode, we need a special quirk to be compiled-in for the RealView platforms. If we find the right compatible string on the GIC TestChip, we enable this quirk by looking up the system controller and enabling the special bits. We depend on the CONFIG_REALVIEW_DT Kconfig symbol as the old boardfile code has the same fix hardcoded, and this is only needed for the attempts to modernize the RealView code using device tree. After fixing this, the PB11MPCore boots with device tree only. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
59 lines
2.7 KiB
Makefile
59 lines
2.7 KiB
Makefile
obj-$(CONFIG_IRQCHIP) += irqchip.o
|
|
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
|
|
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
|
|
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
|
|
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
|
|
obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
|
|
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
|
|
obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
|
|
obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
|
|
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
|
|
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
|
|
obj-$(CONFIG_METAG) += irq-metag-ext.o
|
|
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
|
|
obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o
|
|
obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
|
|
obj-$(CONFIG_OR1K_PIC) += irq-or1k-pic.o
|
|
obj-$(CONFIG_ORION_IRQCHIP) += irq-orion.o
|
|
obj-$(CONFIG_OMAP_IRQCHIP) += irq-omap-intc.o
|
|
obj-$(CONFIG_ARCH_SUNXI) += irq-sun4i.o
|
|
obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi-nmi.o
|
|
obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o
|
|
obj-$(CONFIG_ARM_GIC) += irq-gic.o irq-gic-common.o
|
|
obj-$(CONFIG_REALVIEW_DT) += irq-gic-realview.o
|
|
obj-$(CONFIG_ARM_GIC_V2M) += irq-gic-v2m.o
|
|
obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-common.o
|
|
obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-pci-msi.o irq-gic-v3-its-platform-msi.o
|
|
obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
|
|
obj-$(CONFIG_ARM_VIC) += irq-vic.o
|
|
obj-$(CONFIG_ATMEL_AIC_IRQ) += irq-atmel-aic-common.o irq-atmel-aic.o
|
|
obj-$(CONFIG_ATMEL_AIC5_IRQ) += irq-atmel-aic-common.o irq-atmel-aic5.o
|
|
obj-$(CONFIG_I8259) += irq-i8259.o
|
|
obj-$(CONFIG_IMGPDC_IRQ) += irq-imgpdc.o
|
|
obj-$(CONFIG_IRQ_MIPS_CPU) += irq-mips-cpu.o
|
|
obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o
|
|
obj-$(CONFIG_RENESAS_INTC_IRQPIN) += irq-renesas-intc-irqpin.o
|
|
obj-$(CONFIG_RENESAS_IRQC) += irq-renesas-irqc.o
|
|
obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
|
|
obj-$(CONFIG_ARCH_NSPIRE) += irq-zevio.o
|
|
obj-$(CONFIG_ARCH_VT8500) += irq-vt8500.o
|
|
obj-$(CONFIG_ST_IRQCHIP) += irq-st.o
|
|
obj-$(CONFIG_TB10X_IRQC) += irq-tb10x.o
|
|
obj-$(CONFIG_XTENSA) += irq-xtensa-pic.o
|
|
obj-$(CONFIG_XTENSA_MX) += irq-xtensa-mx.o
|
|
obj-$(CONFIG_IRQ_CROSSBAR) += irq-crossbar.o
|
|
obj-$(CONFIG_SOC_VF610) += irq-vf610-mscm-ir.o
|
|
obj-$(CONFIG_BCM7038_L1_IRQ) += irq-bcm7038-l1.o
|
|
obj-$(CONFIG_BCM7120_L2_IRQ) += irq-bcm7120-l2.o
|
|
obj-$(CONFIG_BRCMSTB_L2_IRQ) += irq-brcmstb-l2.o
|
|
obj-$(CONFIG_KEYSTONE_IRQ) += irq-keystone.o
|
|
obj-$(CONFIG_MIPS_GIC) += irq-mips-gic.o
|
|
obj-$(CONFIG_ARCH_MEDIATEK) += irq-mtk-sysirq.o
|
|
obj-$(CONFIG_ARCH_DIGICOLOR) += irq-digicolor.o
|
|
obj-$(CONFIG_RENESAS_H8300H_INTC) += irq-renesas-h8300h.o
|
|
obj-$(CONFIG_RENESAS_H8S_INTC) += irq-renesas-h8s.o
|
|
obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
|
|
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
|
|
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
|