forked from luck/tmp_suning_uos_patched
8799ee9f49
On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
288 lines
7.5 KiB
ArmAsm
288 lines
7.5 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720
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*
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* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
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* Rob Scott (rscott@mtrob.fdns.net)
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* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd.
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* hacked for non-paged-MM by Hyok S. Choi, 2004.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* These are the low level assembler for performing cache and TLB
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* functions on the ARM720T. The ARM720T has a writethrough IDC
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* cache, so we don't need to clean it.
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*
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* Changelog:
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* 05-09-2000 SJH Created by moving 720 specific functions
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* out of 'proc-arm6,7.S' per RMK discussion
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* 07-25-2000 SJH Added idle function.
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* 08-25-2000 DBS Updated for integration of ARM Ltd version.
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* 04-20-2004 HSC modified for non-paged memory management mode.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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/*
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* Function: arm720_proc_init (void)
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* : arm720_proc_fin (void)
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*
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* Notes : This processor does not require these
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*/
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ENTRY(cpu_arm720_dcache_clean_area)
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ENTRY(cpu_arm720_proc_init)
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mov pc, lr
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ENTRY(cpu_arm720_proc_fin)
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stmfd sp!, {lr}
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mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
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msr cpsr_c, ip
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
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ldmfd sp!, {pc}
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/*
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* Function: arm720_proc_do_idle(void)
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* Params : r0 = unused
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* Purpose : put the processer in proper idle mode
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*/
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ENTRY(cpu_arm720_do_idle)
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mov pc, lr
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/*
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* Function: arm720_switch_mm(unsigned long pgd_phys)
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* Params : pgd_phys Physical address of page table
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* Purpose : Perform a task switch, saving the old process' state and restoring
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* the new.
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*/
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ENTRY(cpu_arm720_switch_mm)
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#ifdef CONFIG_MMU
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mov r1, #0
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mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
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mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
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mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
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#endif
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mov pc, lr
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/*
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* Function: arm720_set_pte(pte_t *ptep, pte_t pte)
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* Params : r0 = Address to set
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* : r1 = value to set
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* Purpose : Set a PTE and flush it out of any WB cache
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*/
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.align 5
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ENTRY(cpu_arm720_set_pte)
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#ifdef CONFIG_MMU
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str r1, [r0], #-2048 @ linux version
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eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r1, #L_PTE_USER @ User?
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orrne r2, r2, #PTE_SMALL_AP_URO_SRW
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tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
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orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
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tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young
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movne r2, #0
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str r2, [r0] @ hardware version
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#endif
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mov pc, lr
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/*
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* Function: arm720_reset
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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ENTRY(cpu_arm720_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x2100 @ ..v....s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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__INIT
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.type __arm710_setup, #function
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__arm710_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
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#endif
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mrc p15, 0, r0, c1, c0 @ get control register
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ldr r5, arm710_cr1_clear
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bic r0, r0, r5
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ldr r5, arm710_cr1_set
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orr r0, r0, r5
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mov pc, lr @ __ret (head.S)
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.size __arm710_setup, . - __arm710_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* .... 0001 ..11 1101
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*
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*/
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.type arm710_cr1_clear, #object
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.type arm710_cr1_set, #object
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arm710_cr1_clear:
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.word 0x0f3f
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arm710_cr1_set:
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.word 0x013d
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.type __arm720_setup, #function
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__arm720_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
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#ifdef CONFIG_MMU
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mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
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#endif
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mrc p15, 0, r0, c1, c0 @ get control register
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ldr r5, arm720_cr1_clear
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bic r0, r0, r5
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ldr r5, arm720_cr1_set
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orr r0, r0, r5
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mov pc, lr @ __ret (head.S)
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.size __arm720_setup, . - __arm720_setup
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/*
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* R
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* .RVI ZFRS BLDP WCAM
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* ..1. 1001 ..11 1101
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*
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*/
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.type arm720_cr1_clear, #object
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.type arm720_cr1_set, #object
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arm720_cr1_clear:
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.word 0x2f3f
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arm720_cr1_set:
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.word 0x213d
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm720_processor_functions, #object
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ENTRY(arm720_processor_functions)
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.word v4t_late_abort
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.word cpu_arm720_proc_init
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.word cpu_arm720_proc_fin
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.word cpu_arm720_reset
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.word cpu_arm720_do_idle
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.word cpu_arm720_dcache_clean_area
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.word cpu_arm720_switch_mm
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.word cpu_arm720_set_pte
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.size arm720_processor_functions, . - arm720_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name: .asciz "armv4t"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name: .asciz "v4"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_arm710_name, #object
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cpu_arm710_name:
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.asciz "ARM710T"
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.size cpu_arm710_name, . - cpu_arm710_name
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.type cpu_arm720_name, #object
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cpu_arm720_name:
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.asciz "ARM720T"
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.size cpu_arm720_name, . - cpu_arm720_name
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.align
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/*
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* See linux/include/asm-arm/procinfo.h for a definition of this structure.
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*/
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.section ".proc.info.init", #alloc, #execinstr
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.type __arm710_proc_info, #object
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__arm710_proc_info:
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.long 0x41807100 @ cpu_val
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.long 0xffffff00 @ cpu_mask
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __arm710_setup @ cpu_flush
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.long cpu_arch_name @ arch_name
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.long cpu_elf_name @ elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap
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.long cpu_arm710_name @ name
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.long arm720_processor_functions
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.long v4_tlb_fns
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.long v4wt_user_fns
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.long v4_cache_fns
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.size __arm710_proc_info, . - __arm710_proc_info
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.type __arm720_proc_info, #object
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__arm720_proc_info:
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.long 0x41807200 @ cpu_val
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.long 0xffffff00 @ cpu_mask
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.long PMD_TYPE_SECT | \
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PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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.long PMD_TYPE_SECT | \
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PMD_BIT4 | \
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PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ
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b __arm720_setup @ cpu_flush
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.long cpu_arch_name @ arch_name
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.long cpu_elf_name @ elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap
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.long cpu_arm720_name @ name
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.long arm720_processor_functions
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.long v4_tlb_fns
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.long v4wt_user_fns
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.long v4_cache_fns
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.size __arm720_proc_info, . - __arm720_proc_info
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