forked from luck/tmp_suning_uos_patched
c8c90860cd
Commit 81d11955bf ("ARM: 6405/1: Handle __flush_icache_all for
CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
flush_icache_all(). It also implemented this for v6 and v7 but not
for v5 and backwards. Without the function pointer in place, we
will be calling wrong cache functions.
For example with ep93xx we get following:
Unable to handle kernel paging request at virtual address ee070f38
pgd = c0004000
[ee070f38] *pgd=00000000
Internal error: Oops: 80000005 [#1] PREEMPT
last sysfs file:
Modules linked in:
CPU: 0 Not tainted (2.6.36+ #1)
PC is at 0xee070f38
LR is at __dma_alloc+0x11c/0x2d0
pc : [<ee070f38>] lr : [<c0032c8c>] psr: 60000013
sp : c581bde0 ip : 00000000 fp : c0472000
r10: c0472000 r9 : 000000d0 r8 : 00020000
r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000
r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: c000717f Table: c0004000 DAC: 00000017
Process swapper (pid: 1, stack limit = 0xc581a270)
[<c0032c8c>] (__dma_alloc+0x11c/0x2d0)
[<c0032e5c>] (dma_alloc_writecombine+0x1c/0x24)
[<c0204148>] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
[<c02041c0>] (ep93xx_pcm_new+0x5c/0x88)
[<c01ff188>] (snd_soc_instantiate_cards+0x8a8/0xbc0)
[<c01ff59c>] (soc_probe+0xfc/0x134)
[<c01adafc>] (platform_drv_probe+0x18/0x1c)
[<c01acca4>] (driver_probe_device+0xb0/0x16c)
[<c01ac284>] (bus_for_each_drv+0x48/0x84)
[<c01ace90>] (device_attach+0x50/0x68)
[<c01ac0f8>] (bus_probe_device+0x24/0x44)
[<c01aad7c>] (device_add+0x2fc/0x44c)
[<c01adfa8>] (platform_device_add+0x104/0x15c)
[<c0015eb8>] (simone_init+0x60/0x94)
[<c0021410>] (do_one_initcall+0xd0/0x1a4)
__dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
calling dmac_flush_range(). Now since the entries in the
arm920_cache_fns are shifted by one, we jump into address 0xee070f38
which is actually next instruction after the arm920_cache_fns
structure.
So implement flush_icache_all() for the rest of the supported CPUs
using a generic 'invalidate I cache' instruction.
Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
696 lines
17 KiB
ArmAsm
696 lines
17 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
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*
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* Heavily based on proc-arm926.S
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* Maintainer: Assaf Hoffman <hoffman@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/*
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* This is the maximum size of an area which will be invalidated
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* using the single invalidate entry instructions. Anything larger
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* than this, and we go for the whole cache.
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*
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* This value should be chosen such that we choose the cheapest
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* alternative.
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*/
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#define CACHE_DLIMIT 16384
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/*
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* the cache line size of the I and D cache
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*/
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#define CACHE_DLINESIZE 32
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.bss
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.align 3
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__cache_params_loc:
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.space 8
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.text
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__cache_params:
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.word __cache_params_loc
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/*
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* cpu_feroceon_proc_init()
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*/
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ENTRY(cpu_feroceon_proc_init)
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mrc p15, 0, r0, c0, c0, 1 @ read cache type register
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ldr r1, __cache_params
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mov r2, #(16 << 5)
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tst r0, #(1 << 16) @ get way
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mov r0, r0, lsr #18 @ get cache size order
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movne r3, #((4 - 1) << 30) @ 4-way
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and r0, r0, #0xf
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moveq r3, #0 @ 1-way
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mov r2, r2, lsl r0 @ actual cache size
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movne r2, r2, lsr #2 @ turned into # of sets
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sub r2, r2, #(1 << 5)
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stmia r1, {r2, r3}
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mov pc, lr
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/*
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* cpu_feroceon_proc_fin()
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*/
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ENTRY(cpu_feroceon_proc_fin)
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#if defined(CONFIG_CACHE_FEROCEON_L2) && \
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!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
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mov r0, #0
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mcr p15, 1, r0, c15, c9, 0 @ clean L2
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x000e @ ............wca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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/*
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* cpu_feroceon_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* loc: location to jump to for soft reset
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*/
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.align 5
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ENTRY(cpu_feroceon_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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#ifdef CONFIG_MMU
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
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#endif
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x000f @ ............wcam
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bic ip, ip, #0x1100 @ ...i...s........
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_feroceon_do_idle()
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*
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* Called with IRQs disabled
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*/
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.align 5
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ENTRY(cpu_feroceon_do_idle)
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(feroceon_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mov pc, lr
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ENDPROC(feroceon_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Clean and invalidate all cache entries in a particular
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* address space.
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(feroceon_flush_kern_cache_all)
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mov r2, #VM_EXEC
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__flush_whole_cache:
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ldr r1, __cache_params
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ldmia r1, {r1, r3}
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1: orr ip, r1, r3
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2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
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subs ip, ip, #(1 << 30) @ next way
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bcs 2b
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subs r1, r1, #(1 << 5) @ next set
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bcs 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Clean and invalidate a range of cache entries in the
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* specified address range.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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.align 5
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ENTRY(feroceon_flush_user_cache_range)
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sub r3, r1, r0 @ calculate total size
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cmp r3, #CACHE_DLIMIT
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bgt __flush_whole_cache
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1: tst r2, #VM_EXEC
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
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mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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tst r2, #VM_EXEC
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mov ip, #0
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(feroceon_coherent_user_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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.align 5
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ENTRY(feroceon_flush_kern_dcache_area)
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add r1, r0, r1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_flush_kern_dcache_area)
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mrs r2, cpsr
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add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* Invalidate (discard) the specified virtual address range.
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* May not write back any entries. If 'start' or 'end'
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* are not cache line aligned, those lines must be written
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* back.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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feroceon_dma_inv_range:
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tst r0, #CACHE_DLINESIZE - 1
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bic r0, r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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feroceon_range_dma_inv_range:
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mrs r2, cpsr
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tst r0, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
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tst r1, #CACHE_DLINESIZE - 1
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c14, 0 @ D inv range start
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mcr p15, 5, r1, c15, c14, 1 @ D inv range top
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msr cpsr_c, r2 @ restore interrupts
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* Clean the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*
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* (same as v4wb)
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*/
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.align 5
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feroceon_dma_clean_range:
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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feroceon_range_dma_clean_range:
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c13, 0 @ D clean range start
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mcr p15, 5, r1, c15, c13, 1 @ D clean range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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.align 5
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ENTRY(feroceon_dma_flush_range)
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bic r0, r0, #CACHE_DLINESIZE - 1
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1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
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add r0, r0, #CACHE_DLINESIZE
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cmp r0, r1
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blo 1b
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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.align 5
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ENTRY(feroceon_range_dma_flush_range)
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mrs r2, cpsr
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cmp r1, r0
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subne r1, r1, #1 @ top address is inclusive
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orr r3, r2, #PSR_I_BIT
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msr cpsr_c, r3 @ disable interrupts
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mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
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mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
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msr cpsr_c, r2 @ restore interrupts
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(feroceon_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq feroceon_dma_clean_range
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bcs feroceon_dma_inv_range
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b feroceon_dma_flush_range
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ENDPROC(feroceon_dma_map_area)
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(feroceon_range_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq feroceon_range_dma_clean_range
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bcs feroceon_range_dma_inv_range
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b feroceon_range_dma_flush_range
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ENDPROC(feroceon_range_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(feroceon_dma_unmap_area)
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mov pc, lr
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ENDPROC(feroceon_dma_unmap_area)
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ENTRY(feroceon_cache_fns)
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.long feroceon_flush_icache_all
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.long feroceon_flush_kern_cache_all
|
|
.long feroceon_flush_user_cache_all
|
|
.long feroceon_flush_user_cache_range
|
|
.long feroceon_coherent_kern_range
|
|
.long feroceon_coherent_user_range
|
|
.long feroceon_flush_kern_dcache_area
|
|
.long feroceon_dma_map_area
|
|
.long feroceon_dma_unmap_area
|
|
.long feroceon_dma_flush_range
|
|
|
|
ENTRY(feroceon_range_cache_fns)
|
|
.long feroceon_flush_icache_all
|
|
.long feroceon_flush_kern_cache_all
|
|
.long feroceon_flush_user_cache_all
|
|
.long feroceon_flush_user_cache_range
|
|
.long feroceon_coherent_kern_range
|
|
.long feroceon_coherent_user_range
|
|
.long feroceon_range_flush_kern_dcache_area
|
|
.long feroceon_range_dma_map_area
|
|
.long feroceon_dma_unmap_area
|
|
.long feroceon_range_dma_flush_range
|
|
|
|
.align 5
|
|
ENTRY(cpu_feroceon_dcache_clean_area)
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
|
|
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
|
|
mov r2, r0
|
|
mov r3, r1
|
|
#endif
|
|
1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
add r0, r0, #CACHE_DLINESIZE
|
|
subs r1, r1, #CACHE_DLINESIZE
|
|
bhi 1b
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
|
|
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
|
|
1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
|
|
add r2, r2, #CACHE_DLINESIZE
|
|
subs r3, r3, #CACHE_DLINESIZE
|
|
bhi 1b
|
|
#endif
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
|
mov pc, lr
|
|
|
|
/* =============================== PageTable ============================== */
|
|
|
|
/*
|
|
* cpu_feroceon_switch_mm(pgd)
|
|
*
|
|
* Set the translation base pointer to be as described by pgd.
|
|
*
|
|
* pgd: new page tables
|
|
*/
|
|
.align 5
|
|
ENTRY(cpu_feroceon_switch_mm)
|
|
#ifdef CONFIG_MMU
|
|
/*
|
|
* Note: we wish to call __flush_whole_cache but we need to preserve
|
|
* lr to do so. The only way without touching main memory is to
|
|
* use r2 which is normally used to test the VM_EXEC flag, and
|
|
* compensate locally for the skipped ops if it is not set.
|
|
*/
|
|
mov r2, lr @ abuse r2 to preserve lr
|
|
bl __flush_whole_cache
|
|
@ if r2 contains the VM_EXEC bit then the next 2 ops are done already
|
|
tst r2, #VM_EXEC
|
|
mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
|
|
mcreq p15, 0, ip, c7, c10, 4 @ drain WB
|
|
|
|
mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
|
|
mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
|
|
mov pc, r2
|
|
#else
|
|
mov pc, lr
|
|
#endif
|
|
|
|
/*
|
|
* cpu_feroceon_set_pte_ext(ptep, pte, ext)
|
|
*
|
|
* Set a PTE and flush it out
|
|
*/
|
|
.align 5
|
|
ENTRY(cpu_feroceon_set_pte_ext)
|
|
#ifdef CONFIG_MMU
|
|
armv3_set_pte_ext wc_disable=0
|
|
mov r0, r0
|
|
mcr p15, 0, r0, c7, c10, 1 @ clean D entry
|
|
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
|
|
!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
|
|
mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
|
|
#endif
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain WB
|
|
#endif
|
|
mov pc, lr
|
|
|
|
__CPUINIT
|
|
|
|
.type __feroceon_setup, #function
|
|
__feroceon_setup:
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
|
|
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
|
|
#ifdef CONFIG_MMU
|
|
mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
|
|
#endif
|
|
|
|
adr r5, feroceon_crval
|
|
ldmia r5, {r5, r6}
|
|
mrc p15, 0, r0, c1, c0 @ get control register v4
|
|
bic r0, r0, r5
|
|
orr r0, r0, r6
|
|
mov pc, lr
|
|
.size __feroceon_setup, . - __feroceon_setup
|
|
|
|
/*
|
|
* B
|
|
* R P
|
|
* .RVI UFRS BLDP WCAM
|
|
* .011 .001 ..11 0101
|
|
*
|
|
*/
|
|
.type feroceon_crval, #object
|
|
feroceon_crval:
|
|
crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
|
|
|
|
__INITDATA
|
|
|
|
/*
|
|
* Purpose : Function pointers used to access above functions - all calls
|
|
* come through these
|
|
*/
|
|
.type feroceon_processor_functions, #object
|
|
feroceon_processor_functions:
|
|
.word v5t_early_abort
|
|
.word legacy_pabort
|
|
.word cpu_feroceon_proc_init
|
|
.word cpu_feroceon_proc_fin
|
|
.word cpu_feroceon_reset
|
|
.word cpu_feroceon_do_idle
|
|
.word cpu_feroceon_dcache_clean_area
|
|
.word cpu_feroceon_switch_mm
|
|
.word cpu_feroceon_set_pte_ext
|
|
.size feroceon_processor_functions, . - feroceon_processor_functions
|
|
|
|
.section ".rodata"
|
|
|
|
.type cpu_arch_name, #object
|
|
cpu_arch_name:
|
|
.asciz "armv5te"
|
|
.size cpu_arch_name, . - cpu_arch_name
|
|
|
|
.type cpu_elf_name, #object
|
|
cpu_elf_name:
|
|
.asciz "v5"
|
|
.size cpu_elf_name, . - cpu_elf_name
|
|
|
|
.type cpu_feroceon_name, #object
|
|
cpu_feroceon_name:
|
|
.asciz "Feroceon"
|
|
.size cpu_feroceon_name, . - cpu_feroceon_name
|
|
|
|
.type cpu_88fr531_name, #object
|
|
cpu_88fr531_name:
|
|
.asciz "Feroceon 88FR531-vd"
|
|
.size cpu_88fr531_name, . - cpu_88fr531_name
|
|
|
|
.type cpu_88fr571_name, #object
|
|
cpu_88fr571_name:
|
|
.asciz "Feroceon 88FR571-vd"
|
|
.size cpu_88fr571_name, . - cpu_88fr571_name
|
|
|
|
.type cpu_88fr131_name, #object
|
|
cpu_88fr131_name:
|
|
.asciz "Feroceon 88FR131"
|
|
.size cpu_88fr131_name, . - cpu_88fr131_name
|
|
|
|
.align
|
|
|
|
.section ".proc.info.init", #alloc, #execinstr
|
|
|
|
#ifdef CONFIG_CPU_FEROCEON_OLD_ID
|
|
.type __feroceon_old_id_proc_info,#object
|
|
__feroceon_old_id_proc_info:
|
|
.long 0x41009260
|
|
.long 0xff00fff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_feroceon_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_cache_fns
|
|
.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
|
|
#endif
|
|
|
|
.type __88fr531_proc_info,#object
|
|
__88fr531_proc_info:
|
|
.long 0x56055310
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_88fr531_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_cache_fns
|
|
.size __88fr531_proc_info, . - __88fr531_proc_info
|
|
|
|
.type __88fr571_proc_info,#object
|
|
__88fr571_proc_info:
|
|
.long 0x56155710
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_88fr571_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_range_cache_fns
|
|
.size __88fr571_proc_info, . - __88fr571_proc_info
|
|
|
|
.type __88fr131_proc_info,#object
|
|
__88fr131_proc_info:
|
|
.long 0x56251310
|
|
.long 0xfffffff0
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_SECT_BUFFERABLE | \
|
|
PMD_SECT_CACHEABLE | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
.long PMD_TYPE_SECT | \
|
|
PMD_BIT4 | \
|
|
PMD_SECT_AP_WRITE | \
|
|
PMD_SECT_AP_READ
|
|
b __feroceon_setup
|
|
.long cpu_arch_name
|
|
.long cpu_elf_name
|
|
.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
|
|
.long cpu_88fr131_name
|
|
.long feroceon_processor_functions
|
|
.long v4wbi_tlb_fns
|
|
.long feroceon_user_fns
|
|
.long feroceon_range_cache_fns
|
|
.size __88fr131_proc_info, . - __88fr131_proc_info
|