forked from luck/tmp_suning_uos_patched
157b6ceb13
* 'x86-iommu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, iommu: Update header comments with appropriate naming ia64, iommu: Add a dummy iommu_table.h file in IA64. x86, iommu: Fix IOMMU_INIT alignment rules x86, doc: Adding comments about .iommu_table and its neighbors. x86, iommu: Utilize the IOMMU_INIT macros functionality. x86, VT-d: Make Intel VT-d IOMMU use IOMMU_INIT_* macros. x86, GART/AMD-VI: Make AMD GART and IOMMU use IOMMU_INIT_* macros. x86, calgary: Make Calgary IOMMU use IOMMU_INIT_* macros. x86, xen-swiotlb: Make Xen-SWIOTLB use IOMMU_INIT_* macros. x86, swiotlb: Make SWIOTLB use IOMMU_INIT_* macros. x86, swiotlb: Simplify SWIOTLB pci_swiotlb_detect routine. x86, iommu: Add proper dependency sort routine (and sanity check). x86, iommu: Make all IOMMU's detection routines return a value. x86, iommu: Add IOMMU_INIT macros, .iommu_table section, and iommu_table_entry structure
114 lines
2.7 KiB
C
114 lines
2.7 KiB
C
#ifndef _ASM_X86_GART_H
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#define _ASM_X86_GART_H
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#include <asm/e820.h>
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extern void set_up_gart_resume(u32, u32);
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extern int fallback_aper_order;
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extern int fallback_aper_force;
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extern int fix_aperture;
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/* PTE bits. */
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#define GPTE_VALID 1
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#define GPTE_COHERENT 2
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/* Aperture control register bits. */
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#define GARTEN (1<<0)
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#define DISGARTCPU (1<<4)
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#define DISGARTIO (1<<5)
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#define DISTLBWALKPRB (1<<6)
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/* GART cache control register bits. */
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#define INVGART (1<<0)
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#define GARTPTEERR (1<<1)
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/* K8 On-cpu GART registers */
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#define AMD64_GARTAPERTURECTL 0x90
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#define AMD64_GARTAPERTUREBASE 0x94
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#define AMD64_GARTTABLEBASE 0x98
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#define AMD64_GARTCACHECTL 0x9c
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#ifdef CONFIG_GART_IOMMU
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extern int gart_iommu_aperture;
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extern int gart_iommu_aperture_allowed;
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extern int gart_iommu_aperture_disabled;
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extern void early_gart_iommu_check(void);
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extern int gart_iommu_init(void);
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extern void __init gart_parse_options(char *);
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extern int gart_iommu_hole_init(void);
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#else
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#define gart_iommu_aperture 0
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#define gart_iommu_aperture_allowed 0
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#define gart_iommu_aperture_disabled 1
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static inline void early_gart_iommu_check(void)
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{
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}
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static inline void gart_parse_options(char *options)
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{
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}
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static inline int gart_iommu_hole_init(void)
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{
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return -ENODEV;
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}
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#endif
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extern int agp_amd64_init(void);
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static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
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{
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u32 ctl;
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/*
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* Don't enable translation but enable GART IO and CPU accesses.
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* Also, set DISTLBWALKPRB since GART tables memory is UC.
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*/
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ctl = DISTLBWALKPRB | order << 1;
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pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
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}
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static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
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{
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u32 tmp, ctl;
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/* address of the mappings table */
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addr >>= 12;
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tmp = (u32) addr<<4;
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tmp &= ~0xf;
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pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
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/* Enable GART translation for this hammer. */
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
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ctl |= GARTEN;
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ctl &= ~(DISGARTCPU | DISGARTIO);
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pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
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}
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static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
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{
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if (!aper_base)
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return 0;
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if (aper_base + aper_size > 0x100000000ULL) {
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printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
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return 0;
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}
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if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
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printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
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return 0;
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}
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if (aper_size < min_size) {
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printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
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aper_size>>20, min_size>>20);
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return 0;
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}
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return 1;
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}
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#endif /* _ASM_X86_GART_H */
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