forked from luck/tmp_suning_uos_patched
f278ea849e
The disabling of the init op for non-legacy clocks neglected to do the same in the core clock framework, resulting in a build failure. Fix it up. Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
359 lines
8.7 KiB
C
359 lines
8.7 KiB
C
/*
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* Helper routines for SuperH Clock Pulse Generator blocks (CPG).
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*
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* Copyright (C) 2010 Magnus Damm
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/clk.h>
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#include <linux/compiler.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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static int sh_clk_mstp32_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
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clk->enable_reg);
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return 0;
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}
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static void sh_clk_mstp32_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
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clk->enable_reg);
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}
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static struct clk_ops sh_clk_mstp32_clk_ops = {
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.enable = sh_clk_mstp32_enable,
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.disable = sh_clk_mstp32_disable,
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.recalc = followparent_recalc,
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};
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int __init sh_clk_mstp32_register(struct clk *clks, int nr)
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{
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struct clk *clkp;
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int ret = 0;
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int k;
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = &sh_clk_mstp32_clk_ops;
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ret |= clk_register(clkp);
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}
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return ret;
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}
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static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_table_round(clk, clk->freq_table, rate);
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}
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static int sh_clk_div6_divisors[64] = {
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1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
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};
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static struct clk_div_mult_table sh_clk_div6_table = {
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.divisors = sh_clk_div6_divisors,
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.nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
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};
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static unsigned long sh_clk_div6_recalc(struct clk *clk)
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{
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struct clk_div_mult_table *table = &sh_clk_div6_table;
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unsigned int idx;
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, NULL);
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idx = __raw_readl(clk->enable_reg) & 0x003f;
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div_mult_table *table = &sh_clk_div6_table;
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u32 value;
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int ret, i;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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value = __raw_readl(clk->enable_reg) &
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~(((1 << clk->src_width) - 1) << clk->src_shift);
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__raw_writel(value | (i << clk->src_shift), clk->enable_reg);
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/* Rebuild the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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return 0;
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}
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static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long value;
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int idx;
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idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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value = __raw_readl(clk->enable_reg);
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value &= ~0x3f;
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value |= idx;
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__raw_writel(value, clk->enable_reg);
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return 0;
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}
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static int sh_clk_div6_enable(struct clk *clk)
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{
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unsigned long value;
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int ret;
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ret = sh_clk_div6_set_rate(clk, clk->rate);
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if (ret == 0) {
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value = __raw_readl(clk->enable_reg);
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value &= ~0x100; /* clear stop bit to enable clock */
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__raw_writel(value, clk->enable_reg);
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}
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return ret;
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}
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static void sh_clk_div6_disable(struct clk *clk)
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{
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unsigned long value;
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value = __raw_readl(clk->enable_reg);
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value |= 0x100; /* stop clock */
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value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
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__raw_writel(value, clk->enable_reg);
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}
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static struct clk_ops sh_clk_div6_clk_ops = {
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.recalc = sh_clk_div6_recalc,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div6_set_rate,
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.enable = sh_clk_div6_enable,
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.disable = sh_clk_div6_disable,
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};
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static struct clk_ops sh_clk_div6_reparent_clk_ops = {
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.recalc = sh_clk_div6_recalc,
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.round_rate = sh_clk_div_round_rate,
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.set_rate = sh_clk_div6_set_rate,
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.enable = sh_clk_div6_enable,
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.disable = sh_clk_div6_disable,
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.set_parent = sh_clk_div6_set_parent,
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};
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static int __init sh_clk_div6_register_ops(struct clk *clks, int nr,
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struct clk_ops *ops)
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{
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struct clk *clkp;
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void *freq_table;
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int nr_divs = sh_clk_div6_table.nr_divisors;
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int freq_table_size = sizeof(struct cpufreq_frequency_table);
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int ret = 0;
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int k;
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freq_table_size *= (nr_divs + 1);
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freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
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if (!freq_table) {
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pr_err("sh_clk_div6_register: unable to alloc memory\n");
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return -ENOMEM;
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}
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = ops;
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clkp->freq_table = freq_table + (k * freq_table_size);
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clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
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ret = clk_register(clkp);
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}
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return ret;
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}
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int __init sh_clk_div6_register(struct clk *clks, int nr)
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{
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return sh_clk_div6_register_ops(clks, nr, &sh_clk_div6_clk_ops);
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}
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int __init sh_clk_div6_reparent_register(struct clk *clks, int nr)
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{
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return sh_clk_div6_register_ops(clks, nr,
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&sh_clk_div6_reparent_clk_ops);
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}
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static unsigned long sh_clk_div4_recalc(struct clk *clk)
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{
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struct clk_div4_table *d4t = clk->priv;
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struct clk_div_mult_table *table = d4t->div_mult_table;
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unsigned int idx;
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
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return clk->freq_table[idx].frequency;
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}
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static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
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{
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struct clk_div4_table *d4t = clk->priv;
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struct clk_div_mult_table *table = d4t->div_mult_table;
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u32 value;
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int ret;
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/* we really need a better way to determine parent index, but for
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* now assume internal parent comes with CLK_ENABLE_ON_INIT set,
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* no CLK_ENABLE_ON_INIT means external clock...
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*/
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if (parent->flags & CLK_ENABLE_ON_INIT)
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value = __raw_readl(clk->enable_reg) & ~(1 << 7);
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else
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value = __raw_readl(clk->enable_reg) | (1 << 7);
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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__raw_writel(value, clk->enable_reg);
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/* Rebiuld the frequency table */
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clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
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table, &clk->arch_flags);
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return 0;
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}
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static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
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{
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struct clk_div4_table *d4t = clk->priv;
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unsigned long value;
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int idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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value = __raw_readl(clk->enable_reg);
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value &= ~(0xf << clk->enable_bit);
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value |= (idx << clk->enable_bit);
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__raw_writel(value, clk->enable_reg);
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if (d4t->kick)
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d4t->kick(clk);
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return 0;
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}
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static int sh_clk_div4_enable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
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return 0;
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}
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static void sh_clk_div4_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
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}
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static struct clk_ops sh_clk_div4_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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};
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static struct clk_ops sh_clk_div4_enable_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div4_enable,
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.disable = sh_clk_div4_disable,
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};
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static struct clk_ops sh_clk_div4_reparent_clk_ops = {
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.recalc = sh_clk_div4_recalc,
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.set_rate = sh_clk_div4_set_rate,
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.round_rate = sh_clk_div_round_rate,
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.enable = sh_clk_div4_enable,
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.disable = sh_clk_div4_disable,
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.set_parent = sh_clk_div4_set_parent,
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};
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static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
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struct clk_div4_table *table, struct clk_ops *ops)
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{
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struct clk *clkp;
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void *freq_table;
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int nr_divs = table->div_mult_table->nr_divisors;
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int freq_table_size = sizeof(struct cpufreq_frequency_table);
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int ret = 0;
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int k;
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freq_table_size *= (nr_divs + 1);
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freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
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if (!freq_table) {
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pr_err("sh_clk_div4_register: unable to alloc memory\n");
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return -ENOMEM;
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}
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for (k = 0; !ret && (k < nr); k++) {
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clkp = clks + k;
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clkp->ops = ops;
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clkp->priv = table;
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clkp->freq_table = freq_table + (k * freq_table_size);
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clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
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ret = clk_register(clkp);
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}
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return ret;
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}
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int __init sh_clk_div4_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
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}
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int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table,
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&sh_clk_div4_enable_clk_ops);
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}
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int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
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struct clk_div4_table *table)
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{
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return sh_clk_div4_register_ops(clks, nr, table,
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&sh_clk_div4_reparent_clk_ops);
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}
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