forked from luck/tmp_suning_uos_patched
8b8d2b658f
AER is a PCIe-only capability, so there's no point in trying to match a HEST PCIe structure with a non-PCIe device. Previously, a HEST global AER bridge entry (type 8) could incorrectly match *any* bridge, even a legacy PCI-PCI bridge, and a non-global HEST entry could match a legacy PCI device. Tested-by: Betty Dall <betty.dall@hp.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> |
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.. | ||
aer | ||
aspm.c | ||
Kconfig | ||
Makefile | ||
pme.c | ||
portdrv_acpi.c | ||
portdrv_bus.c | ||
portdrv_core.c | ||
portdrv_pci.c | ||
portdrv.h |