forked from luck/tmp_suning_uos_patched
39273b58a4
Make sure the restoration correctly restores the AR registers by flipping the ARX register into index mode before doing anything. Without this, some people have had the text mode restore all green. Signed-off-by: Jesse Barnes <jesse.barnes@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
598 lines
17 KiB
C
598 lines
17 KiB
C
/* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "drm_pciids.h"
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static struct pci_device_id pciidlist[] = {
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i915_PCI_IDS
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};
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enum pipe {
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PIPE_A = 0,
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PIPE_B,
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};
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static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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if (pipe == PIPE_A)
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return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
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else
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return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
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}
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static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
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u32 *array;
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int i;
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if (!i915_pipe_enabled(dev, pipe))
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return;
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if (pipe == PIPE_A)
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array = dev_priv->save_palette_a;
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else
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array = dev_priv->save_palette_b;
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for(i = 0; i < 256; i++)
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array[i] = I915_READ(reg + (i << 2));
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}
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static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
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u32 *array;
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int i;
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if (!i915_pipe_enabled(dev, pipe))
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return;
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if (pipe == PIPE_A)
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array = dev_priv->save_palette_a;
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else
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array = dev_priv->save_palette_b;
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for(i = 0; i < 256; i++)
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I915_WRITE(reg + (i << 2), array[i]);
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}
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static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
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{
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outb(reg, index_port);
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return inb(data_port);
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}
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static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
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{
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inb(st01);
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outb(palette_enable | reg, VGA_AR_INDEX);
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return inb(VGA_AR_DATA_READ);
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}
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static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
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{
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inb(st01);
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outb(palette_enable | reg, VGA_AR_INDEX);
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outb(val, VGA_AR_DATA_WRITE);
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}
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static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
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{
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outb(reg, index_port);
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outb(val, data_port);
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}
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static void i915_save_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* VGA color palette registers */
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dev_priv->saveDACMASK = inb(VGA_DACMASK);
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/* DACCRX automatically increments during read */
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outb(0, VGA_DACRX);
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/* Read 3 bytes of color data from each index */
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for (i = 0; i < 256 * 3; i++)
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dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
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/* MSR bits */
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dev_priv->saveMSR = inb(VGA_MSR_READ);
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if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* CRT controller regs */
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i915_write_indexed(cr_index, cr_data, 0x11,
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i915_read_indexed(cr_index, cr_data, 0x11) &
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(~0x80));
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for (i = 0; i < 0x24; i++)
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dev_priv->saveCR[i] =
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i915_read_indexed(cr_index, cr_data, i);
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/* Make sure we don't turn off CR group 0 writes */
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dev_priv->saveCR[0x11] &= ~0x80;
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/* Attribute controller registers */
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inb(st01);
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dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
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for (i = 0; i < 20; i++)
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dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
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inb(st01);
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outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
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inb(st01);
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/* Graphics controller registers */
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for (i = 0; i < 9; i++)
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dev_priv->saveGR[i] =
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i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
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dev_priv->saveGR[0x10] =
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i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
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dev_priv->saveGR[0x11] =
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i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
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dev_priv->saveGR[0x18] =
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i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
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/* Sequencer registers */
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for (i = 0; i < 8; i++)
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dev_priv->saveSR[i] =
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i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
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}
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static void i915_restore_vga(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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u16 cr_index, cr_data, st01;
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/* MSR bits */
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outb(dev_priv->saveMSR, VGA_MSR_WRITE);
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if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
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cr_index = VGA_CR_INDEX_CGA;
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cr_data = VGA_CR_DATA_CGA;
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st01 = VGA_ST01_CGA;
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} else {
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cr_index = VGA_CR_INDEX_MDA;
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cr_data = VGA_CR_DATA_MDA;
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st01 = VGA_ST01_MDA;
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}
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/* Sequencer registers, don't write SR07 */
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for (i = 0; i < 7; i++)
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i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
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dev_priv->saveSR[i]);
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/* CRT controller regs */
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/* Enable CR group 0 writes */
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i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
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for (i = 0; i < 0x24; i++)
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i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
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/* Graphics controller regs */
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for (i = 0; i < 9; i++)
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i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
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dev_priv->saveGR[i]);
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i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
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dev_priv->saveGR[0x10]);
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i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
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dev_priv->saveGR[0x11]);
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i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
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dev_priv->saveGR[0x18]);
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/* Attribute controller registers */
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inb(st01);
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for (i = 0; i < 20; i++)
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i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
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inb(st01); /* switch back to index mode */
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outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
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inb(st01);
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/* VGA color palette registers */
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outb(dev_priv->saveDACMASK, VGA_DACMASK);
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/* DACCRX automatically increments during read */
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outb(0, VGA_DACWX);
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/* Read 3 bytes of color data from each index */
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for (i = 0; i < 256 * 3; i++)
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outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
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}
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static int i915_suspend(struct drm_device *dev, pm_message_t state)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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if (!dev || !dev_priv) {
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printk(KERN_ERR "dev: %p, dev_priv: %p\n", dev, dev_priv);
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printk(KERN_ERR "DRM not initialized, aborting suspend.\n");
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return -ENODEV;
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}
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if (state.event == PM_EVENT_PRETHAW)
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return 0;
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pci_save_state(dev->pdev);
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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dev_priv->saveFPA0 = I915_READ(FPA0);
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dev_priv->saveFPA1 = I915_READ(FPA1);
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dev_priv->saveDPLL_A = I915_READ(DPLL_A);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
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dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
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dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
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dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
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dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
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dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
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dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
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dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
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dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
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dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
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dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
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dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
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dev_priv->saveDSPABASE = I915_READ(DSPABASE);
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if (IS_I965G(dev)) {
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dev_priv->saveDSPASURF = I915_READ(DSPASURF);
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dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
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}
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i915_save_palette(dev, PIPE_A);
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dev_priv->savePIPEASTAT = I915_READ(I915REG_PIPEASTAT);
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/* Pipe & plane B info */
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dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
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dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
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dev_priv->saveFPB0 = I915_READ(FPB0);
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dev_priv->saveFPB1 = I915_READ(FPB1);
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dev_priv->saveDPLL_B = I915_READ(DPLL_B);
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if (IS_I965G(dev))
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dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
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dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
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dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
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dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
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dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
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dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
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dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
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dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
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dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
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dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
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dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
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dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
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dev_priv->saveDSPBBASE = I915_READ(DSPBBASE);
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if (IS_I965GM(dev) || IS_IGD_GM(dev)) {
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dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
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dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
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}
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i915_save_palette(dev, PIPE_B);
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dev_priv->savePIPEBSTAT = I915_READ(I915REG_PIPEBSTAT);
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/* CRT state */
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dev_priv->saveADPA = I915_READ(ADPA);
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/* LVDS state */
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dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
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dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
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dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
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if (IS_I965G(dev))
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dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
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if (IS_MOBILE(dev) && !IS_I830(dev))
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dev_priv->saveLVDS = I915_READ(LVDS);
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if (!IS_I830(dev) && !IS_845G(dev))
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dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
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dev_priv->saveLVDSPP_ON = I915_READ(LVDSPP_ON);
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dev_priv->saveLVDSPP_OFF = I915_READ(LVDSPP_OFF);
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dev_priv->savePP_CYCLE = I915_READ(PP_CYCLE);
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/* FIXME: save TV & SDVO state */
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/* FBC state */
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dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
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dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
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dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
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dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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/* Interrupt state */
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dev_priv->saveIIR = I915_READ(I915REG_INT_IDENTITY_R);
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dev_priv->saveIER = I915_READ(I915REG_INT_ENABLE_R);
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dev_priv->saveIMR = I915_READ(I915REG_INT_MASK_R);
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/* VGA state */
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dev_priv->saveVCLK_DIVISOR_VGA0 = I915_READ(VCLK_DIVISOR_VGA0);
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dev_priv->saveVCLK_DIVISOR_VGA1 = I915_READ(VCLK_DIVISOR_VGA1);
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dev_priv->saveVCLK_POST_DIV = I915_READ(VCLK_POST_DIV);
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dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
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/* Clock gating state */
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dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
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/* Cache mode state */
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dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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/* Memory Arbitration state */
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dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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/* Scratch space */
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for (i = 0; i < 16; i++) {
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dev_priv->saveSWF0[i] = I915_READ(SWF0 + (i << 2));
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dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
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}
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for (i = 0; i < 3; i++)
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dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
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i915_save_vga(dev);
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if (state.event == PM_EVENT_SUSPEND) {
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/* Shut down the device */
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pci_disable_device(dev->pdev);
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pci_set_power_state(dev->pdev, PCI_D3hot);
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}
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return 0;
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}
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static int i915_resume(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_set_power_state(dev->pdev, PCI_D0);
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pci_restore_state(dev->pdev);
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if (pci_enable_device(dev->pdev))
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return -1;
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pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
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/* Pipe & plane A info */
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/* Prime the clock */
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if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
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~DPLL_VCO_ENABLE);
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udelay(150);
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}
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I915_WRITE(FPA0, dev_priv->saveFPA0);
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I915_WRITE(FPA1, dev_priv->saveFPA1);
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/* Actually enable it */
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I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
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udelay(150);
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if (IS_I965G(dev))
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I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
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udelay(150);
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/* Restore mode */
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I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
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I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
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I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
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I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
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I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
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I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
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I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
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/* Restore plane info */
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I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
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I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
|
|
I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
|
|
I915_WRITE(DSPABASE, dev_priv->saveDSPABASE);
|
|
I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
|
|
if (IS_I965G(dev)) {
|
|
I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
|
|
I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
|
|
}
|
|
|
|
I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
|
|
|
|
i915_restore_palette(dev, PIPE_A);
|
|
/* Enable the plane */
|
|
I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
|
|
I915_WRITE(DSPABASE, I915_READ(DSPABASE));
|
|
|
|
/* Pipe & plane B info */
|
|
if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
|
|
I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
|
|
~DPLL_VCO_ENABLE);
|
|
udelay(150);
|
|
}
|
|
I915_WRITE(FPB0, dev_priv->saveFPB0);
|
|
I915_WRITE(FPB1, dev_priv->saveFPB1);
|
|
/* Actually enable it */
|
|
I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
|
|
udelay(150);
|
|
if (IS_I965G(dev))
|
|
I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
|
|
udelay(150);
|
|
|
|
/* Restore mode */
|
|
I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
|
|
I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
|
|
I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
|
|
I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
|
|
I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
|
|
I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
|
|
I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
|
|
|
|
/* Restore plane info */
|
|
I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
|
|
I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
|
|
I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
|
|
I915_WRITE(DSPBBASE, dev_priv->saveDSPBBASE);
|
|
I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
|
|
if (IS_I965G(dev)) {
|
|
I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
|
|
I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
|
|
}
|
|
|
|
I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
|
|
|
|
i915_restore_palette(dev, PIPE_B);
|
|
/* Enable the plane */
|
|
I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
|
|
I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
|
|
|
|
/* CRT state */
|
|
I915_WRITE(ADPA, dev_priv->saveADPA);
|
|
|
|
/* LVDS state */
|
|
if (IS_I965G(dev))
|
|
I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
|
|
if (IS_MOBILE(dev) && !IS_I830(dev))
|
|
I915_WRITE(LVDS, dev_priv->saveLVDS);
|
|
if (!IS_I830(dev) && !IS_845G(dev))
|
|
I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
|
|
|
|
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
|
|
I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
|
|
I915_WRITE(LVDSPP_ON, dev_priv->saveLVDSPP_ON);
|
|
I915_WRITE(LVDSPP_OFF, dev_priv->saveLVDSPP_OFF);
|
|
I915_WRITE(PP_CYCLE, dev_priv->savePP_CYCLE);
|
|
I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
|
|
|
|
/* FIXME: restore TV & SDVO state */
|
|
|
|
/* FBC info */
|
|
I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
|
|
I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
|
|
I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
|
|
I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
|
|
|
|
/* VGA state */
|
|
I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
|
|
I915_WRITE(VCLK_DIVISOR_VGA0, dev_priv->saveVCLK_DIVISOR_VGA0);
|
|
I915_WRITE(VCLK_DIVISOR_VGA1, dev_priv->saveVCLK_DIVISOR_VGA1);
|
|
I915_WRITE(VCLK_POST_DIV, dev_priv->saveVCLK_POST_DIV);
|
|
udelay(150);
|
|
|
|
/* Clock gating state */
|
|
I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
|
|
|
|
/* Cache mode state */
|
|
I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
|
|
|
|
/* Memory arbitration state */
|
|
I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
I915_WRITE(SWF0 + (i << 2), dev_priv->saveSWF0[i]);
|
|
I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
|
|
}
|
|
for (i = 0; i < 3; i++)
|
|
I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
|
|
|
|
i915_restore_vga(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_driver driver = {
|
|
/* don't use mtrr's here, the Xserver or user space app should
|
|
* deal with them for intel hardware.
|
|
*/
|
|
.driver_features =
|
|
DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
|
|
DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL |
|
|
DRIVER_IRQ_VBL2,
|
|
.load = i915_driver_load,
|
|
.unload = i915_driver_unload,
|
|
.lastclose = i915_driver_lastclose,
|
|
.preclose = i915_driver_preclose,
|
|
.suspend = i915_suspend,
|
|
.resume = i915_resume,
|
|
.device_is_agp = i915_driver_device_is_agp,
|
|
.vblank_wait = i915_driver_vblank_wait,
|
|
.vblank_wait2 = i915_driver_vblank_wait2,
|
|
.irq_preinstall = i915_driver_irq_preinstall,
|
|
.irq_postinstall = i915_driver_irq_postinstall,
|
|
.irq_uninstall = i915_driver_irq_uninstall,
|
|
.irq_handler = i915_driver_irq_handler,
|
|
.reclaim_buffers = drm_core_reclaim_buffers,
|
|
.get_map_ofs = drm_core_get_map_ofs,
|
|
.get_reg_ofs = drm_core_get_reg_ofs,
|
|
.ioctls = i915_ioctls,
|
|
.fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.ioctl = drm_ioctl,
|
|
.mmap = drm_mmap,
|
|
.poll = drm_poll,
|
|
.fasync = drm_fasync,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = i915_compat_ioctl,
|
|
#endif
|
|
},
|
|
|
|
.pci_driver = {
|
|
.name = DRIVER_NAME,
|
|
.id_table = pciidlist,
|
|
},
|
|
|
|
.name = DRIVER_NAME,
|
|
.desc = DRIVER_DESC,
|
|
.date = DRIVER_DATE,
|
|
.major = DRIVER_MAJOR,
|
|
.minor = DRIVER_MINOR,
|
|
.patchlevel = DRIVER_PATCHLEVEL,
|
|
};
|
|
|
|
static int __init i915_init(void)
|
|
{
|
|
driver.num_ioctls = i915_max_ioctl;
|
|
return drm_init(&driver);
|
|
}
|
|
|
|
static void __exit i915_exit(void)
|
|
{
|
|
drm_exit(&driver);
|
|
}
|
|
|
|
module_init(i915_init);
|
|
module_exit(i915_exit);
|
|
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_LICENSE("GPL and additional rights");
|