forked from luck/tmp_suning_uos_patched
3108e6ab21
This does two things to the FPGA IRQ controller in the versatile family: - Convert to MULTI_IRQ_HANDLER so we can drop the entry macro from the Integrator. The C IRQ handler was inspired from arch/arm/common/vic.c, recent bug discovered in this handler was accounted for. - Convert to using IRQ domains so we can get rid of the NO_IRQ mess and proceed with device tree and such stuff. As part of the exercise, bump all the low IRQ numbers on the Integrator PIC to start from 1 rather than 0, since IRQ 0 is now NO_IRQ. The Linux IRQ numbers are thus entirely decoupled from the hardware IRQ numbers in this controller. I was unable to split this patch. The main reason is the half-done conversion to device tree in Versatile. Tested on Integrator/AP and Integrator/CP. Cc: Grant Likely <grant.likely@secretlab.ca> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
159 lines
4.0 KiB
C
159 lines
4.0 KiB
C
/*
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* Support for Versatile FPGA-based IRQ controllers
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*/
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <plat/fpga-irq.h>
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#define IRQ_STATUS 0x00
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#define IRQ_RAW_STATUS 0x04
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#define IRQ_ENABLE_SET 0x08
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#define IRQ_ENABLE_CLEAR 0x0c
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/**
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* struct fpga_irq_data - irq data container for the FPGA IRQ controller
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* @base: memory offset in virtual memory
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* @irq_start: first IRQ number handled by this instance
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* @chip: chip container for this instance
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* @domain: IRQ domain for this instance
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* @valid: mask for valid IRQs on this controller
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* @used_irqs: number of active IRQs on this controller
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*/
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struct fpga_irq_data {
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void __iomem *base;
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unsigned int irq_start;
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struct irq_chip chip;
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u32 valid;
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struct irq_domain *domain;
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u8 used_irqs;
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};
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/* we cannot allocate memory when the controllers are initially registered */
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static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
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static int fpga_irq_id;
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static void fpga_irq_mask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << d->hwirq;
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writel(mask, f->base + IRQ_ENABLE_CLEAR);
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}
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static void fpga_irq_unmask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << d->hwirq;
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writel(mask, f->base + IRQ_ENABLE_SET);
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}
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static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
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{
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struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
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u32 status = readl(f->base + IRQ_STATUS);
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if (status == 0) {
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do_bad_IRQ(irq, desc);
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return;
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}
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do {
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irq = ffs(status) - 1;
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status &= ~(1 << irq);
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generic_handle_irq(irq_find_mapping(f->domain, irq));
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} while (status);
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}
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/*
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* Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
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* if we've handled at least one interrupt. This does a single read of the
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* status register and handles all interrupts in order from LSB first.
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*/
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static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
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{
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int handled = 0;
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int irq;
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u32 status;
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while ((status = readl(f->base + IRQ_STATUS))) {
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irq = ffs(status) - 1;
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handle_IRQ(irq_find_mapping(f->domain, irq), regs);
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handled = 1;
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}
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return handled;
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}
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/*
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* Keep iterating over all registered FPGA IRQ controllers until there are
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* no pending interrupts.
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*/
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asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
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{
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int i, handled;
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do {
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for (i = 0, handled = 0; i < fpga_irq_id; ++i)
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handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
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} while (handled);
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}
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static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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struct fpga_irq_data *f = d->host_data;
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/* Skip invalid IRQs, only register handlers for the real ones */
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if (!(f->valid & (1 << hwirq)))
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return -ENOTSUPP;
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irq_set_chip_data(irq, f);
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irq_set_chip_and_handler(irq, &f->chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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f->used_irqs++;
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return 0;
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}
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static struct irq_domain_ops fpga_irqdomain_ops = {
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.map = fpga_irqdomain_map,
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.xlate = irq_domain_xlate_onetwocell,
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};
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void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
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int parent_irq, u32 valid, struct device_node *node)
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{
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struct fpga_irq_data *f;
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if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
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printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
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return;
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}
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f = &fpga_irq_devices[fpga_irq_id];
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f->base = base;
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f->irq_start = irq_start;
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f->chip.name = name;
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f->chip.irq_ack = fpga_irq_mask;
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f->chip.irq_mask = fpga_irq_mask;
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f->chip.irq_unmask = fpga_irq_unmask;
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f->valid = valid;
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if (parent_irq != -1) {
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irq_set_handler_data(parent_irq, f);
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irq_set_chained_handler(parent_irq, fpga_irq_handle);
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}
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f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
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&fpga_irqdomain_ops, f);
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pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
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fpga_irq_id, name, base, f->used_irqs);
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fpga_irq_id++;
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}
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