forked from luck/tmp_suning_uos_patched
52c543f90c
This patch adds the foundation pieces for the Freescale MXC platforms, including i.MX2 and i.MX3 based systems. The bare-bones MX31 support in this patch boots to the rootdev panic with 8250 serial console configured "console=ttyS0,115200". It assumes that Redboot is the boot loader. Signed-off-by: Quinn Jensen <quinn.jensen@freescale.com> Acked-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
153 lines
4.0 KiB
C
153 lines
4.0 KiB
C
/*
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* System Timer Interrupt reconfigured to run in free-run mode.
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* Author: Vitaly Wool
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* Copyright 2004 MontaVista Software Inc.
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/*!
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* @file time.c
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* @brief This file contains OS tick and wdog timer implementations.
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*
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* This file contains OS tick and wdog timer implementations.
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*
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* @ingroup Timers
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach/time.h>
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#include <asm/io.h>
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#include <asm/arch/common.h>
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/*!
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* This is the timer interrupt service routine to do required tasks.
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* It also services the WDOG timer at the frequency of twice per WDOG
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* timeout value. For example, if the WDOG's timeout value is 4 (2
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* seconds since the WDOG runs at 0.5Hz), it will be serviced once
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* every 2/2=1 second.
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*
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* @param irq GPT interrupt source number (not used)
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* @param dev_id this parameter is not used
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* @return always returns \b IRQ_HANDLED as defined in
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* include/linux/interrupt.h.
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*/
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static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
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{
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unsigned int next_match;
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write_seqlock(&xtime_lock);
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if (__raw_readl(MXC_GPT_GPTSR) & GPTSR_OF1) {
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do {
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timer_tick();
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next_match = __raw_readl(MXC_GPT_GPTOCR1) + LATCH;
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__raw_writel(GPTSR_OF1, MXC_GPT_GPTSR);
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__raw_writel(next_match, MXC_GPT_GPTOCR1);
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} while ((signed long)(next_match -
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__raw_readl(MXC_GPT_GPTCNT)) <= 0);
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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/*!
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* This function is used to obtain the number of microseconds since the last
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* timer interrupt. Note that interrupts is disabled by do_gettimeofday().
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*
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* @return the number of microseconds since the last timer interrupt.
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*/
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static unsigned long mxc_gettimeoffset(void)
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{
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unsigned long ticks_to_match, elapsed, usec, tick_usec, i;
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/* Get ticks before next timer match */
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ticks_to_match =
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__raw_readl(MXC_GPT_GPTOCR1) - __raw_readl(MXC_GPT_GPTCNT);
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/* We need elapsed ticks since last match */
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elapsed = LATCH - ticks_to_match;
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/* Now convert them to usec */
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/* Insure no overflow when calculating the usec below */
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for (i = 1, tick_usec = tick_nsec / 1000;; i *= 2) {
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tick_usec /= i;
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if ((0xFFFFFFFF / tick_usec) > elapsed)
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break;
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}
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usec = (unsigned long)(elapsed * tick_usec) / (LATCH / i);
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return usec;
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}
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/*!
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* The OS tick timer interrupt structure.
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*/
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static struct irqaction timer_irq = {
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.name = "MXC Timer Tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = mxc_timer_interrupt
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};
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/*!
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* This function is used to initialize the GPT to produce an interrupt
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* based on HZ. It is called by start_kernel() during system startup.
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*/
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void __init mxc_init_time(void)
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{
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u32 reg, v;
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reg = __raw_readl(MXC_GPT_GPTCR);
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reg &= ~GPTCR_ENABLE;
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__raw_writel(reg, MXC_GPT_GPTCR);
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reg |= GPTCR_SWR;
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__raw_writel(reg, MXC_GPT_GPTCR);
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while ((__raw_readl(MXC_GPT_GPTCR) & GPTCR_SWR) != 0)
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cpu_relax();
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reg = GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ;
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__raw_writel(reg, MXC_GPT_GPTCR);
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/* TODO: get timer rate from clk driver */
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v = 66500000;
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__raw_writel((v / CLOCK_TICK_RATE) - 1, MXC_GPT_GPTPR);
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if ((v % CLOCK_TICK_RATE) != 0) {
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pr_info("\nWARNING: Can't generate CLOCK_TICK_RATE at %d Hz\n",
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CLOCK_TICK_RATE);
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}
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pr_info("Actual CLOCK_TICK_RATE is %d Hz\n",
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v / ((__raw_readl(MXC_GPT_GPTPR) & 0xFFF) + 1));
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reg = __raw_readl(MXC_GPT_GPTCNT);
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reg += LATCH;
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__raw_writel(reg, MXC_GPT_GPTOCR1);
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setup_irq(MXC_INT_GPT, &timer_irq);
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reg = __raw_readl(MXC_GPT_GPTCR);
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reg =
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GPTCR_FRR | GPTCR_CLKSRC_HIGHFREQ | GPTCR_STOPEN | GPTCR_DOZEN |
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GPTCR_WAITEN | GPTCR_ENMOD | GPTCR_ENABLE;
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__raw_writel(reg, MXC_GPT_GPTCR);
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__raw_writel(GPTIR_OF1IE, MXC_GPT_GPTIR);
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}
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struct sys_timer mxc_timer = {
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.init = mxc_init_time,
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.offset = mxc_gettimeoffset,
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};
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