forked from luck/tmp_suning_uos_patched
a7db504052
This was #define'd as 0 on all platforms, so let's get rid of it. This change makes pci_scan_slot() slightly easier to read. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Tony Luck <tony.luck@intel.com> Cc: David Howells <dhowells@redhat.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jeff Dike <jdike@addtoit.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Acked-by: Russell King <linux@arm.linux.org.uk> Acked-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: Kyle McMartin <kyle@mcmartin.ca> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Paul Mundt <lethal@linux-sh.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
277 lines
8.7 KiB
C
277 lines
8.7 KiB
C
#ifndef __ALPHA_PCI_H
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#define __ALPHA_PCI_H
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#ifdef __KERNEL__
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#include <linux/spinlock.h>
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#include <linux/dma-mapping.h>
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#include <asm/scatterlist.h>
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#include <asm/machvec.h>
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/*
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* The following structure is used to manage multiple PCI busses.
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*/
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struct pci_dev;
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struct pci_bus;
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struct resource;
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struct pci_iommu_arena;
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struct page;
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/* A controller. Used to manage multiple PCI busses. */
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struct pci_controller {
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struct pci_controller *next;
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struct pci_bus *bus;
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struct resource *io_space;
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struct resource *mem_space;
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/* The following are for reporting to userland. The invariant is
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that if we report a BWX-capable dense memory, we do not report
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a sparse memory at all, even if it exists. */
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unsigned long sparse_mem_base;
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unsigned long dense_mem_base;
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unsigned long sparse_io_base;
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unsigned long dense_io_base;
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/* This one's for the kernel only. It's in KSEG somewhere. */
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unsigned long config_space_base;
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unsigned int index;
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/* For compatibility with current (as of July 2003) pciutils
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and XFree86. Eventually will be removed. */
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unsigned int need_domain_info;
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struct pci_iommu_arena *sg_pci;
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struct pci_iommu_arena *sg_isa;
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void *sysdata;
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};
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/* Override the logic in pci_scan_bus for skipping already-configured
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bus numbers. */
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO alpha_mv.min_io_address
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#define PCIBIOS_MIN_MEM alpha_mv.min_mem_address
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extern void pcibios_set_master(struct pci_dev *dev);
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extern inline void pcibios_penalize_isa_irq(int irq, int active)
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{
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/* We don't do dynamic PCI IRQ allocation */
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}
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/* IOMMU controls. */
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/* The PCI address space does not equal the physical memory address space.
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The networking and block device layers use this boolean for bounce buffer
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decisions. */
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#define PCI_DMA_BUS_IS_PHYS 0
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/* Allocate and map kernel buffer using consistent mode DMA for PCI
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device. Returns non-NULL cpu-view pointer to the buffer if
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successful and sets *DMA_ADDRP to the pci side dma address as well,
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else DMA_ADDRP is undefined. */
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extern void *__pci_alloc_consistent(struct pci_dev *, size_t,
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dma_addr_t *, gfp_t);
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static inline void *
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pci_alloc_consistent(struct pci_dev *dev, size_t size, dma_addr_t *dma)
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{
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return __pci_alloc_consistent(dev, size, dma, GFP_ATOMIC);
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}
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/* Free and unmap a consistent DMA buffer. CPU_ADDR and DMA_ADDR must
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be values that were returned from pci_alloc_consistent. SIZE must
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be the same as what as passed into pci_alloc_consistent.
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References to the memory and mappings associated with CPU_ADDR or
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DMA_ADDR past this call are illegal. */
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extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t);
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/* Map a single buffer of the indicate size for PCI DMA in streaming mode.
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The 32-bit PCI bus mastering address to use is returned. Once the device
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is given the dma address, the device owns this memory until either
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pci_unmap_single or pci_dma_sync_single_for_cpu is performed. */
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extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int);
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/* Likewise, but for a page instead of an address. */
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extern dma_addr_t pci_map_page(struct pci_dev *, struct page *,
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unsigned long, size_t, int);
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/* Test for pci_map_single or pci_map_page having generated an error. */
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static inline int
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pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr)
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{
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return dma_addr == 0;
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}
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/* Unmap a single streaming mode DMA translation. The DMA_ADDR and
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SIZE must match what was provided for in a previous pci_map_single
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call. All other usages are undefined. After this call, reads by
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the cpu to the buffer are guaranteed to see whatever the device
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wrote there. */
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extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int);
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extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int);
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/* pci_unmap_{single,page} is not a nop, thus... */
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#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
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dma_addr_t ADDR_NAME;
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#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
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__u32 LEN_NAME;
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#define pci_unmap_addr(PTR, ADDR_NAME) \
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((PTR)->ADDR_NAME)
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#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
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(((PTR)->ADDR_NAME) = (VAL))
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#define pci_unmap_len(PTR, LEN_NAME) \
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((PTR)->LEN_NAME)
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#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
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(((PTR)->LEN_NAME) = (VAL))
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/* Map a set of buffers described by scatterlist in streaming mode for
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PCI DMA. This is the scatter-gather version of the above
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pci_map_single interface. Here the scatter gather list elements
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are each tagged with the appropriate PCI dma address and length.
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They are obtained via sg_dma_{address,length}(SG).
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NOTE: An implementation may be able to use a smaller number of DMA
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address/length pairs than there are SG table elements. (for
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example via virtual mapping capabilities) The routine returns the
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number of addr/length pairs actually used, at most nents.
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Device ownership issues as mentioned above for pci_map_single are
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the same here. */
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extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int);
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/* Unmap a set of streaming mode DMA translations. Again, cpu read
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rules concerning calls here are the same as for pci_unmap_single()
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above. */
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extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int);
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/* Make physical memory consistent for a single streaming mode DMA
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translation after a transfer and device currently has ownership
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of the buffer.
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If you perform a pci_map_single() but wish to interrogate the
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buffer using the cpu, yet do not wish to teardown the PCI dma
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mapping, you must call this function before doing so. At the next
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point you give the PCI dma address back to the card, you must first
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perform a pci_dma_sync_for_device, and then the device again owns
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the buffer. */
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static inline void
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pci_dma_sync_single_for_cpu(struct pci_dev *dev, dma_addr_t dma_addr,
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long size, int direction)
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{
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/* Nothing to do. */
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}
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static inline void
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pci_dma_sync_single_for_device(struct pci_dev *dev, dma_addr_t dma_addr,
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size_t size, int direction)
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{
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/* Nothing to do. */
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}
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/* Make physical memory consistent for a set of streaming mode DMA
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translations after a transfer. The same as pci_dma_sync_single_*
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but for a scatter-gather list, same rules and usage. */
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static inline void
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pci_dma_sync_sg_for_cpu(struct pci_dev *dev, struct scatterlist *sg,
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int nents, int direction)
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{
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/* Nothing to do. */
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}
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static inline void
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pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg,
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int nents, int direction)
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{
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/* Nothing to do. */
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}
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/* Return whether the given PCI device DMA address mask can
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be supported properly. For example, if your device can
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only drive the low 24-bits during PCI bus mastering, then
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you would pass 0x00ffffff as the mask to this function. */
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extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
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#ifdef CONFIG_PCI
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static inline void pci_dma_burst_advice(struct pci_dev *pdev,
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enum pci_dma_burst_strategy *strat,
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unsigned long *strategy_parameter)
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{
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unsigned long cacheline_size;
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u8 byte;
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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*strat = PCI_DMA_BURST_BOUNDARY;
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*strategy_parameter = cacheline_size;
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}
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#endif
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/* TODO: integrate with include/asm-generic/pci.h ? */
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static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
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{
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return channel ? 15 : 14;
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}
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extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
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struct resource *);
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extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region);
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#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
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static inline int pci_proc_domain(struct pci_bus *bus)
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{
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struct pci_controller *hose = bus->sysdata;
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return hose->need_domain_info;
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}
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struct pci_dev *alpha_gendev_to_pci(struct device *dev);
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#endif /* __KERNEL__ */
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/* Values for the `which' argument to sys_pciconfig_iobase. */
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#define IOBASE_HOSE 0
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#define IOBASE_SPARSE_MEM 1
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#define IOBASE_DENSE_MEM 2
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#define IOBASE_SPARSE_IO 3
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#define IOBASE_DENSE_IO 4
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#define IOBASE_ROOT_BUS 5
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#define IOBASE_FROM_HOSE 0x10000
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extern struct pci_dev *isa_bridge;
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extern int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val,
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size_t count);
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extern int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val,
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size_t count);
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extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
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struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state);
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extern void pci_adjust_legacy_attr(struct pci_bus *bus,
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enum pci_mmap_state mmap_type);
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#define HAVE_PCI_LEGACY 1
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extern int pci_create_resource_files(struct pci_dev *dev);
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extern void pci_remove_resource_files(struct pci_dev *dev);
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#endif /* __ALPHA_PCI_H */
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