forked from luck/tmp_suning_uos_patched
5856d8bd30
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20200719153822.59788-1-grandmaster@al2klimov.de
Signed-off-by: Mark Brown <broonie@kernel.org>
220 lines
9.2 KiB
C
220 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Texas Instruments PCM186x Universal Audio ADC
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*
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* Copyright (C) 2015-2017 Texas Instruments Incorporated - https://www.ti.com
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* Andreas Dannenberg <dannenberg@ti.com>
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* Andrew F. Davis <afd@ti.com>
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*/
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#ifndef _PCM186X_H_
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#define _PCM186X_H_
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#include <linux/pm.h>
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#include <linux/regmap.h>
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enum pcm186x_type {
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PCM1862,
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PCM1863,
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PCM1864,
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PCM1865,
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};
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#define PCM186X_RATES SNDRV_PCM_RATE_8000_192000
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#define PCM186X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
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SNDRV_PCM_FMTBIT_S20_3LE |\
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SNDRV_PCM_FMTBIT_S24_LE | \
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SNDRV_PCM_FMTBIT_S32_LE)
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#define PCM186X_PAGE_LEN 0x0100
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#define PCM186X_PAGE_BASE(n) (PCM186X_PAGE_LEN * n)
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/* The page selection register address is the same on all pages */
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#define PCM186X_PAGE 0
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/* Register Definitions - Page 0 */
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#define PCM186X_PGA_VAL_CH1_L (PCM186X_PAGE_BASE(0) + 1)
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#define PCM186X_PGA_VAL_CH1_R (PCM186X_PAGE_BASE(0) + 2)
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#define PCM186X_PGA_VAL_CH2_L (PCM186X_PAGE_BASE(0) + 3)
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#define PCM186X_PGA_VAL_CH2_R (PCM186X_PAGE_BASE(0) + 4)
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#define PCM186X_PGA_CTRL (PCM186X_PAGE_BASE(0) + 5)
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#define PCM186X_ADC1_INPUT_SEL_L (PCM186X_PAGE_BASE(0) + 6)
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#define PCM186X_ADC1_INPUT_SEL_R (PCM186X_PAGE_BASE(0) + 7)
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#define PCM186X_ADC2_INPUT_SEL_L (PCM186X_PAGE_BASE(0) + 8)
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#define PCM186X_ADC2_INPUT_SEL_R (PCM186X_PAGE_BASE(0) + 9)
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#define PCM186X_AUXADC_INPUT_SEL (PCM186X_PAGE_BASE(0) + 10)
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#define PCM186X_PCM_CFG (PCM186X_PAGE_BASE(0) + 11)
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#define PCM186X_TDM_TX_SEL (PCM186X_PAGE_BASE(0) + 12)
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#define PCM186X_TDM_TX_OFFSET (PCM186X_PAGE_BASE(0) + 13)
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#define PCM186X_TDM_RX_OFFSET (PCM186X_PAGE_BASE(0) + 14)
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#define PCM186X_DPGA_VAL_CH1_L (PCM186X_PAGE_BASE(0) + 15)
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#define PCM186X_GPIO1_0_CTRL (PCM186X_PAGE_BASE(0) + 16)
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#define PCM186X_GPIO3_2_CTRL (PCM186X_PAGE_BASE(0) + 17)
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#define PCM186X_GPIO1_0_DIR_CTRL (PCM186X_PAGE_BASE(0) + 18)
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#define PCM186X_GPIO3_2_DIR_CTRL (PCM186X_PAGE_BASE(0) + 19)
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#define PCM186X_GPIO_IN_OUT (PCM186X_PAGE_BASE(0) + 20)
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#define PCM186X_GPIO_PULL_CTRL (PCM186X_PAGE_BASE(0) + 21)
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#define PCM186X_DPGA_VAL_CH1_R (PCM186X_PAGE_BASE(0) + 22)
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#define PCM186X_DPGA_VAL_CH2_L (PCM186X_PAGE_BASE(0) + 23)
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#define PCM186X_DPGA_VAL_CH2_R (PCM186X_PAGE_BASE(0) + 24)
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#define PCM186X_DPGA_GAIN_CTRL (PCM186X_PAGE_BASE(0) + 25)
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#define PCM186X_DPGA_MIC_CTRL (PCM186X_PAGE_BASE(0) + 26)
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#define PCM186X_DIN_RESAMP_CTRL (PCM186X_PAGE_BASE(0) + 27)
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#define PCM186X_CLK_CTRL (PCM186X_PAGE_BASE(0) + 32)
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#define PCM186X_DSP1_CLK_DIV (PCM186X_PAGE_BASE(0) + 33)
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#define PCM186X_DSP2_CLK_DIV (PCM186X_PAGE_BASE(0) + 34)
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#define PCM186X_ADC_CLK_DIV (PCM186X_PAGE_BASE(0) + 35)
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#define PCM186X_PLL_SCK_DIV (PCM186X_PAGE_BASE(0) + 37)
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#define PCM186X_BCK_DIV (PCM186X_PAGE_BASE(0) + 38)
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#define PCM186X_LRK_DIV (PCM186X_PAGE_BASE(0) + 39)
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#define PCM186X_PLL_CTRL (PCM186X_PAGE_BASE(0) + 40)
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#define PCM186X_PLL_P_DIV (PCM186X_PAGE_BASE(0) + 41)
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#define PCM186X_PLL_R_DIV (PCM186X_PAGE_BASE(0) + 42)
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#define PCM186X_PLL_J_DIV (PCM186X_PAGE_BASE(0) + 43)
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#define PCM186X_PLL_D_DIV_LSB (PCM186X_PAGE_BASE(0) + 44)
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#define PCM186X_PLL_D_DIV_MSB (PCM186X_PAGE_BASE(0) + 45)
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#define PCM186X_SIGDET_MODE (PCM186X_PAGE_BASE(0) + 48)
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#define PCM186X_SIGDET_MASK (PCM186X_PAGE_BASE(0) + 49)
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#define PCM186X_SIGDET_STAT (PCM186X_PAGE_BASE(0) + 50)
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#define PCM186X_SIGDET_LOSS_TIME (PCM186X_PAGE_BASE(0) + 52)
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#define PCM186X_SIGDET_SCAN_TIME (PCM186X_PAGE_BASE(0) + 53)
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#define PCM186X_SIGDET_INT_INTVL (PCM186X_PAGE_BASE(0) + 54)
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#define PCM186X_SIGDET_DC_REF_CH1_L (PCM186X_PAGE_BASE(0) + 64)
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#define PCM186X_SIGDET_DC_DIFF_CH1_L (PCM186X_PAGE_BASE(0) + 65)
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#define PCM186X_SIGDET_DC_LEV_CH1_L (PCM186X_PAGE_BASE(0) + 66)
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#define PCM186X_SIGDET_DC_REF_CH1_R (PCM186X_PAGE_BASE(0) + 67)
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#define PCM186X_SIGDET_DC_DIFF_CH1_R (PCM186X_PAGE_BASE(0) + 68)
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#define PCM186X_SIGDET_DC_LEV_CH1_R (PCM186X_PAGE_BASE(0) + 69)
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#define PCM186X_SIGDET_DC_REF_CH2_L (PCM186X_PAGE_BASE(0) + 70)
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#define PCM186X_SIGDET_DC_DIFF_CH2_L (PCM186X_PAGE_BASE(0) + 71)
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#define PCM186X_SIGDET_DC_LEV_CH2_L (PCM186X_PAGE_BASE(0) + 72)
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#define PCM186X_SIGDET_DC_REF_CH2_R (PCM186X_PAGE_BASE(0) + 73)
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#define PCM186X_SIGDET_DC_DIFF_CH2_R (PCM186X_PAGE_BASE(0) + 74)
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#define PCM186X_SIGDET_DC_LEV_CH2_R (PCM186X_PAGE_BASE(0) + 75)
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#define PCM186X_SIGDET_DC_REF_CH3_L (PCM186X_PAGE_BASE(0) + 76)
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#define PCM186X_SIGDET_DC_DIFF_CH3_L (PCM186X_PAGE_BASE(0) + 77)
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#define PCM186X_SIGDET_DC_LEV_CH3_L (PCM186X_PAGE_BASE(0) + 78)
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#define PCM186X_SIGDET_DC_REF_CH3_R (PCM186X_PAGE_BASE(0) + 79)
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#define PCM186X_SIGDET_DC_DIFF_CH3_R (PCM186X_PAGE_BASE(0) + 80)
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#define PCM186X_SIGDET_DC_LEV_CH3_R (PCM186X_PAGE_BASE(0) + 81)
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#define PCM186X_SIGDET_DC_REF_CH4_L (PCM186X_PAGE_BASE(0) + 82)
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#define PCM186X_SIGDET_DC_DIFF_CH4_L (PCM186X_PAGE_BASE(0) + 83)
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#define PCM186X_SIGDET_DC_LEV_CH4_L (PCM186X_PAGE_BASE(0) + 84)
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#define PCM186X_SIGDET_DC_REF_CH4_R (PCM186X_PAGE_BASE(0) + 85)
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#define PCM186X_SIGDET_DC_DIFF_CH4_R (PCM186X_PAGE_BASE(0) + 86)
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#define PCM186X_SIGDET_DC_LEV_CH4_R (PCM186X_PAGE_BASE(0) + 87)
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#define PCM186X_AUXADC_DATA_CTRL (PCM186X_PAGE_BASE(0) + 88)
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#define PCM186X_AUXADC_DATA_LSB (PCM186X_PAGE_BASE(0) + 89)
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#define PCM186X_AUXADC_DATA_MSB (PCM186X_PAGE_BASE(0) + 90)
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#define PCM186X_INT_ENABLE (PCM186X_PAGE_BASE(0) + 96)
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#define PCM186X_INT_FLAG (PCM186X_PAGE_BASE(0) + 97)
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#define PCM186X_INT_POL_WIDTH (PCM186X_PAGE_BASE(0) + 98)
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#define PCM186X_POWER_CTRL (PCM186X_PAGE_BASE(0) + 112)
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#define PCM186X_FILTER_MUTE_CTRL (PCM186X_PAGE_BASE(0) + 113)
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#define PCM186X_DEVICE_STATUS (PCM186X_PAGE_BASE(0) + 114)
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#define PCM186X_FSAMPLE_STATUS (PCM186X_PAGE_BASE(0) + 115)
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#define PCM186X_DIV_STATUS (PCM186X_PAGE_BASE(0) + 116)
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#define PCM186X_CLK_STATUS (PCM186X_PAGE_BASE(0) + 117)
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#define PCM186X_SUPPLY_STATUS (PCM186X_PAGE_BASE(0) + 120)
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/* Register Definitions - Page 1 */
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#define PCM186X_MMAP_STAT_CTRL (PCM186X_PAGE_BASE(1) + 1)
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#define PCM186X_MMAP_ADDRESS (PCM186X_PAGE_BASE(1) + 2)
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#define PCM186X_MEM_WDATA0 (PCM186X_PAGE_BASE(1) + 4)
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#define PCM186X_MEM_WDATA1 (PCM186X_PAGE_BASE(1) + 5)
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#define PCM186X_MEM_WDATA2 (PCM186X_PAGE_BASE(1) + 6)
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#define PCM186X_MEM_WDATA3 (PCM186X_PAGE_BASE(1) + 7)
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#define PCM186X_MEM_RDATA0 (PCM186X_PAGE_BASE(1) + 8)
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#define PCM186X_MEM_RDATA1 (PCM186X_PAGE_BASE(1) + 9)
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#define PCM186X_MEM_RDATA2 (PCM186X_PAGE_BASE(1) + 10)
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#define PCM186X_MEM_RDATA3 (PCM186X_PAGE_BASE(1) + 11)
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/* Register Definitions - Page 3 */
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#define PCM186X_OSC_PWR_DOWN_CTRL (PCM186X_PAGE_BASE(3) + 18)
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#define PCM186X_MIC_BIAS_CTRL (PCM186X_PAGE_BASE(3) + 21)
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/* Register Definitions - Page 253 */
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#define PCM186X_CURR_TRIM_CTRL (PCM186X_PAGE_BASE(253) + 20)
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#define PCM186X_MAX_REGISTER PCM186X_CURR_TRIM_CTRL
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/* PCM186X_PAGE */
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#define PCM186X_RESET 0xfe
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/* PCM186X_ADCX_INPUT_SEL_X */
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#define PCM186X_ADC_INPUT_SEL_POL BIT(7)
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#define PCM186X_ADC_INPUT_SEL_MASK GENMASK(5, 0)
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/* PCM186X_PCM_CFG */
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#define PCM186X_PCM_CFG_RX_WLEN_MASK GENMASK(7, 6)
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#define PCM186X_PCM_CFG_RX_WLEN_SHIFT 6
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#define PCM186X_PCM_CFG_RX_WLEN_32 0x00
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#define PCM186X_PCM_CFG_RX_WLEN_24 0x01
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#define PCM186X_PCM_CFG_RX_WLEN_20 0x02
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#define PCM186X_PCM_CFG_RX_WLEN_16 0x03
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#define PCM186X_PCM_CFG_TDM_LRCK_MODE BIT(4)
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#define PCM186X_PCM_CFG_TX_WLEN_MASK GENMASK(3, 2)
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#define PCM186X_PCM_CFG_TX_WLEN_SHIFT 2
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#define PCM186X_PCM_CFG_TX_WLEN_32 0x00
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#define PCM186X_PCM_CFG_TX_WLEN_24 0x01
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#define PCM186X_PCM_CFG_TX_WLEN_20 0x02
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#define PCM186X_PCM_CFG_TX_WLEN_16 0x03
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#define PCM186X_PCM_CFG_FMT_MASK GENMASK(1, 0)
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#define PCM186X_PCM_CFG_FMT_SHIFT 0
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#define PCM186X_PCM_CFG_FMT_I2S 0x00
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#define PCM186X_PCM_CFG_FMT_LEFTJ 0x01
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#define PCM186X_PCM_CFG_FMT_RIGHTJ 0x02
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#define PCM186X_PCM_CFG_FMT_TDM 0x03
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/* PCM186X_TDM_TX_SEL */
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#define PCM186X_TDM_TX_SEL_2CH 0x00
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#define PCM186X_TDM_TX_SEL_4CH 0x01
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#define PCM186X_TDM_TX_SEL_6CH 0x02
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#define PCM186X_TDM_TX_SEL_MASK 0x03
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/* PCM186X_CLK_CTRL */
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#define PCM186X_CLK_CTRL_SCK_XI_SEL1 BIT(7)
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#define PCM186X_CLK_CTRL_SCK_XI_SEL0 BIT(6)
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#define PCM186X_CLK_CTRL_SCK_SRC_PLL BIT(5)
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#define PCM186X_CLK_CTRL_MST_MODE BIT(4)
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#define PCM186X_CLK_CTRL_ADC_SRC_PLL BIT(3)
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#define PCM186X_CLK_CTRL_DSP2_SRC_PLL BIT(2)
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#define PCM186X_CLK_CTRL_DSP1_SRC_PLL BIT(1)
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#define PCM186X_CLK_CTRL_CLKDET_EN BIT(0)
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/* PCM186X_PLL_CTRL */
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#define PCM186X_PLL_CTRL_LOCK BIT(4)
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#define PCM186X_PLL_CTRL_REF_SEL BIT(1)
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#define PCM186X_PLL_CTRL_EN BIT(0)
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/* PCM186X_POWER_CTRL */
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#define PCM186X_PWR_CTRL_PWRDN BIT(2)
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#define PCM186X_PWR_CTRL_SLEEP BIT(1)
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#define PCM186X_PWR_CTRL_STBY BIT(0)
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/* PCM186X_CLK_STATUS */
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#define PCM186X_CLK_STATUS_LRCKHLT BIT(6)
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#define PCM186X_CLK_STATUS_BCKHLT BIT(5)
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#define PCM186X_CLK_STATUS_SCKHLT BIT(4)
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#define PCM186X_CLK_STATUS_LRCKERR BIT(2)
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#define PCM186X_CLK_STATUS_BCKERR BIT(1)
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#define PCM186X_CLK_STATUS_SCKERR BIT(0)
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/* PCM186X_SUPPLY_STATUS */
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#define PCM186X_SUPPLY_STATUS_DVDD BIT(2)
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#define PCM186X_SUPPLY_STATUS_AVDD BIT(1)
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#define PCM186X_SUPPLY_STATUS_LDO BIT(0)
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/* PCM186X_MMAP_STAT_CTRL */
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#define PCM186X_MMAP_STAT_DONE BIT(4)
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#define PCM186X_MMAP_STAT_BUSY BIT(2)
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#define PCM186X_MMAP_STAT_R_REQ BIT(1)
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#define PCM186X_MMAP_STAT_W_REQ BIT(0)
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extern const struct regmap_config pcm186x_regmap;
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int pcm186x_probe(struct device *dev, enum pcm186x_type type, int irq,
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struct regmap *regmap);
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#endif /* _PCM186X_H_ */
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