forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
128 lines
2.2 KiB
ArmAsm
128 lines
2.2 KiB
ArmAsm
/*
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* linux/arch/arm26/lib/io-writesw.S
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*
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* Copyright (C) 1995-2000 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/hardware.h>
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.outsw_bad_alignment:
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adr r0, .outsw_bad_align_msg
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mov r2, lr
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b panic
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.outsw_bad_align_msg:
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.asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
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.align
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.outsw_align: tst r1, #1
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bne .outsw_bad_alignment
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add r1, r1, #2
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ldr r3, [r1, #-4]
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mov r3, r3, lsr #16
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orr r3, r3, r3, lsl #16
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str r3, [r0]
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subs r2, r2, #1
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RETINSTR(moveq, pc, lr)
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ENTRY(__raw_writesw)
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teq r2, #0 @ do we have to check for the zero len?
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moveq pc, lr
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tst r1, #3
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bne .outsw_align
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.outsw_aligned: stmfd sp!, {r4, r5, r6, lr}
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subs r2, r2, #8
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bmi .no_outsw_8
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.outsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
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mov ip, r3, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r3, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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mov ip, r4, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r4, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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mov ip, r5, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r5, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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mov ip, r6, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r6, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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subs r2, r2, #8
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bpl .outsw_8_lp
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tst r2, #7
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LOADREGS(eqfd, sp!, {r4, r5, r6, pc})
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.no_outsw_8: tst r2, #4
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beq .no_outsw_4
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ldmia r1!, {r3, r4}
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mov ip, r3, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r3, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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mov ip, r4, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r4, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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.no_outsw_4: tst r2, #2
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beq .no_outsw_2
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ldr r3, [r1], #4
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mov ip, r3, lsl #16
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orr ip, ip, ip, lsr #16
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str ip, [r0]
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mov ip, r3, lsr #16
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orr ip, ip, ip, lsl #16
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str ip, [r0]
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.no_outsw_2: tst r2, #1
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ldrne r3, [r1]
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movne ip, r3, lsl #16
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orrne ip, ip, ip, lsr #16
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strne ip, [r0]
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LOADREGS(fd, sp!, {r4, r5, r6, pc})
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