forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
160 lines
4.5 KiB
C
160 lines
4.5 KiB
C
/*
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* PowerPC64 SLB support.
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*
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* Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
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* Based on earlier code writteh by:
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* Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
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* Copyright (c) 2001 Dave Engebretsen
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* Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/mmu_context.h>
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#include <asm/paca.h>
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#include <asm/cputable.h>
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extern void slb_allocate(unsigned long ea);
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static inline unsigned long mk_esid_data(unsigned long ea, unsigned long slot)
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{
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return (ea & ESID_MASK) | SLB_ESID_V | slot;
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}
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static inline unsigned long mk_vsid_data(unsigned long ea, unsigned long flags)
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{
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return (get_kernel_vsid(ea) << SLB_VSID_SHIFT) | flags;
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}
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static inline void create_slbe(unsigned long ea, unsigned long vsid,
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unsigned long flags, unsigned long entry)
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{
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asm volatile("slbmte %0,%1" :
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: "r" (mk_vsid_data(ea, flags)),
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"r" (mk_esid_data(ea, entry))
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: "memory" );
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}
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static void slb_flush_and_rebolt(void)
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{
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/* If you change this make sure you change SLB_NUM_BOLTED
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* appropriately too. */
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unsigned long ksp_flags = SLB_VSID_KERNEL;
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unsigned long ksp_esid_data;
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WARN_ON(!irqs_disabled());
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if (cpu_has_feature(CPU_FTR_16M_PAGE))
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ksp_flags |= SLB_VSID_L;
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ksp_esid_data = mk_esid_data(get_paca()->kstack, 2);
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if ((ksp_esid_data & ESID_MASK) == KERNELBASE)
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ksp_esid_data &= ~SLB_ESID_V;
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/* We need to do this all in asm, so we're sure we don't touch
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* the stack between the slbia and rebolting it. */
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asm volatile("isync\n"
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"slbia\n"
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/* Slot 1 - first VMALLOC segment */
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"slbmte %0,%1\n"
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/* Slot 2 - kernel stack */
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"slbmte %2,%3\n"
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"isync"
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:: "r"(mk_vsid_data(VMALLOCBASE, SLB_VSID_KERNEL)),
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"r"(mk_esid_data(VMALLOCBASE, 1)),
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"r"(mk_vsid_data(ksp_esid_data, ksp_flags)),
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"r"(ksp_esid_data)
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: "memory");
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}
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/* Flush all user entries from the segment table of the current processor. */
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void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
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{
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unsigned long offset = get_paca()->slb_cache_ptr;
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unsigned long esid_data = 0;
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unsigned long pc = KSTK_EIP(tsk);
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unsigned long stack = KSTK_ESP(tsk);
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unsigned long unmapped_base;
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if (offset <= SLB_CACHE_ENTRIES) {
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int i;
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asm volatile("isync" : : : "memory");
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for (i = 0; i < offset; i++) {
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esid_data = (unsigned long)get_paca()->slb_cache[i]
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<< SID_SHIFT;
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asm volatile("slbie %0" : : "r" (esid_data));
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}
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asm volatile("isync" : : : "memory");
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} else {
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slb_flush_and_rebolt();
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}
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/* Workaround POWER5 < DD2.1 issue */
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if (offset == 1 || offset > SLB_CACHE_ENTRIES)
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asm volatile("slbie %0" : : "r" (esid_data));
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get_paca()->slb_cache_ptr = 0;
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get_paca()->context = mm->context;
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/*
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* preload some userspace segments into the SLB.
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*/
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if (test_tsk_thread_flag(tsk, TIF_32BIT))
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unmapped_base = TASK_UNMAPPED_BASE_USER32;
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else
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unmapped_base = TASK_UNMAPPED_BASE_USER64;
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if (pc >= KERNELBASE)
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return;
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slb_allocate(pc);
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if (GET_ESID(pc) == GET_ESID(stack))
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return;
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if (stack >= KERNELBASE)
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return;
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slb_allocate(stack);
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if ((GET_ESID(pc) == GET_ESID(unmapped_base))
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|| (GET_ESID(stack) == GET_ESID(unmapped_base)))
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return;
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if (unmapped_base >= KERNELBASE)
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return;
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slb_allocate(unmapped_base);
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}
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void slb_initialize(void)
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{
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/* On iSeries the bolted entries have already been set up by
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* the hypervisor from the lparMap data in head.S */
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#ifndef CONFIG_PPC_ISERIES
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unsigned long flags = SLB_VSID_KERNEL;
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/* Invalidate the entire SLB (even slot 0) & all the ERATS */
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if (cpu_has_feature(CPU_FTR_16M_PAGE))
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flags |= SLB_VSID_L;
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asm volatile("isync":::"memory");
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asm volatile("slbmte %0,%0"::"r" (0) : "memory");
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asm volatile("isync; slbia; isync":::"memory");
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create_slbe(KERNELBASE, get_kernel_vsid(KERNELBASE), flags, 0);
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create_slbe(VMALLOCBASE, get_kernel_vsid(KERNELBASE),
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SLB_VSID_KERNEL, 1);
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/* We don't bolt the stack for the time being - we're in boot,
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* so the stack is in the bolted segment. By the time it goes
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* elsewhere, we'll call _switch() which will bolt in the new
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* one. */
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asm volatile("isync":::"memory");
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#endif
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get_paca()->stab_rr = SLB_NUM_BOLTED;
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}
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