forked from luck/tmp_suning_uos_patched
92704a1c63
On uniprocessor, it's always zero for optimize that. On SMP, the jmpl to the stub kills the return address stack in the cpu branch prediction logic, so expand the code sequence inline and use a code patching section to fix things up. This also always better and explicit register selection, which will be taken advantage of in a future changeset. The hard_smp_processor_id() function is big, so do not inline it. Fix up tests for Jalapeno to also test for Serrano chips too. These tests want "jbus Ultra-IIIi" cases to match, so that is what we should test for. Signed-off-by: David S. Miller <davem@davemloft.net>
64 lines
1.7 KiB
C
64 lines
1.7 KiB
C
/* $Id: head.h,v 1.30 1997/08/08 08:34:33 jj Exp $ */
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#ifndef _SPARC64_HEAD_H
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#define _SPARC64_HEAD_H
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#include <asm/pstate.h>
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#define KERNBASE 0x400000
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#define PTREGS_OFF (STACK_BIAS + STACKFRAME_SZ)
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#define __CHEETAH_ID 0x003e0014
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#define __JALAPENO_ID 0x003e0016
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#define __SERRANO_ID 0x003e0022
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#define CHEETAH_MANUF 0x003e
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#define CHEETAH_IMPL 0x0014 /* Ultra-III */
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#define CHEETAH_PLUS_IMPL 0x0015 /* Ultra-III+ */
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#define JALAPENO_IMPL 0x0016 /* Ultra-IIIi */
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#define JAGUAR_IMPL 0x0018 /* Ultra-IV */
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#define PANTHER_IMPL 0x0019 /* Ultra-IV+ */
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#define SERRANO_IMPL 0x0022 /* Ultra-IIIi+ */
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#define BRANCH_IF_CHEETAH_BASE(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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sethi %hi(__CHEETAH_ID), %tmp2; \
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srlx %tmp1, 32, %tmp1; \
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or %tmp2, %lo(__CHEETAH_ID), %tmp2;\
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cmp %tmp1, %tmp2; \
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be,pn %icc, label; \
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nop;
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#define BRANCH_IF_JALAPENO(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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sethi %hi(__JALAPENO_ID), %tmp2; \
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srlx %tmp1, 32, %tmp1; \
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or %tmp2, %lo(__JALAPENO_ID), %tmp2;\
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cmp %tmp1, %tmp2; \
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be,pn %icc, label; \
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nop;
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#define BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_MANUF; \
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bne,pt %xcc, 99f; \
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sllx %tmp1, 16, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_PLUS_IMPL; \
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bgeu,pt %xcc, label; \
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99: nop;
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#define BRANCH_IF_ANY_CHEETAH(tmp1,tmp2,label) \
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rdpr %ver, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_MANUF; \
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bne,pt %xcc, 99f; \
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sllx %tmp1, 16, %tmp1; \
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srlx %tmp1, (32 + 16), %tmp2; \
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cmp %tmp2, CHEETAH_IMPL; \
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bgeu,pt %xcc, label; \
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99: nop;
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#endif /* !(_SPARC64_HEAD_H) */
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