forked from luck/tmp_suning_uos_patched
8e958839e4
The "SRMMU" supports 4k pages using a fixed three-level walk with a
256-entry PGD and 64-entry PMD/PTE levels. In order to fill a page
with a 'pgtable_t', the SRMMU code allocates four native PTE tables
into a single PTE allocation and similarly for the PMD level, leading
to an array of 16 physical pointers in a 'pmd_t'
This breaks the generic code which assumes READ_ONCE(*pmd) will be
word sized.
In a manner similar to ef22d8abd8 ("m68k: mm: Restructure Motorola
MMU page-table layout"), this patch implements the native page-table
setup directly. This significantly increases the page-table memory
overhead, but will be addresses in a subsequent patch.
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Peter Zijlstra <peterz@infradead.org>
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
285 lines
6.0 KiB
ArmAsm
285 lines
6.0 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* viking.S: High speed Viking cache/mmu operations
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*
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* Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
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* Copyright (C) 1997,1998,1999 Jakub Jelinek (jj@ultra.linux.cz)
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* Copyright (C) 1999 Pavel Semerad (semerad@ss1000.ms.mff.cuni.cz)
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*/
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#include <asm/ptrace.h>
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#include <asm/psr.h>
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#include <asm/asm-offsets.h>
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#include <asm/asi.h>
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#include <asm/mxcc.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/pgtsrmmu.h>
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#include <asm/viking.h>
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#ifdef CONFIG_SMP
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.data
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.align 4
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sun4dsmp_flush_tlb_spin:
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.word 0
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#endif
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.text
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.align 4
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.globl viking_flush_cache_all, viking_flush_cache_mm
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.globl viking_flush_cache_range, viking_flush_cache_page
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.globl viking_flush_page, viking_mxcc_flush_page
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.globl viking_flush_page_for_dma, viking_flush_page_to_ram
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.globl viking_flush_sig_insns
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.globl viking_flush_tlb_all, viking_flush_tlb_mm
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.globl viking_flush_tlb_range, viking_flush_tlb_page
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viking_flush_page:
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sethi %hi(PAGE_OFFSET), %g2
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sub %o0, %g2, %g3
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srl %g3, 12, %g1 ! ppage >> 12
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clr %o1 ! set counter, 0 - 127
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sethi %hi(PAGE_OFFSET + PAGE_SIZE - 0x80000000), %o3
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sethi %hi(0x80000000), %o4
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sethi %hi(VIKING_PTAG_VALID), %o5
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sethi %hi(2*PAGE_SIZE), %o0
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sethi %hi(PAGE_SIZE), %g7
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clr %o2 ! block counter, 0 - 3
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5:
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sll %o1, 5, %g4
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or %g4, %o4, %g4 ! 0x80000000 | (set << 5)
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sll %o2, 26, %g5 ! block << 26
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6:
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or %g5, %g4, %g5
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ldda [%g5] ASI_M_DATAC_TAG, %g2
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cmp %g3, %g1 ! ptag == ppage?
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bne 7f
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inc %o2
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andcc %g2, %o5, %g0 ! ptag VALID?
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be 7f
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add %g4, %o3, %g2 ! (PAGE_OFFSET + PAGE_SIZE) | (set << 5)
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ld [%g2], %g3
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ld [%g2 + %g7], %g3
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add %g2, %o0, %g2
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ld [%g2], %g3
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ld [%g2 + %g7], %g3
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add %g2, %o0, %g2
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ld [%g2], %g3
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ld [%g2 + %g7], %g3
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add %g2, %o0, %g2
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ld [%g2], %g3
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b 8f
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ld [%g2 + %g7], %g3
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7:
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cmp %o2, 3
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ble 6b
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sll %o2, 26, %g5 ! block << 26
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8: inc %o1
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cmp %o1, 0x7f
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ble 5b
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clr %o2
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9: retl
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nop
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viking_mxcc_flush_page:
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sethi %hi(PAGE_OFFSET), %g2
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sub %o0, %g2, %g3
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sub %g3, -PAGE_SIZE, %g3 ! ppage + PAGE_SIZE
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sethi %hi(MXCC_SRCSTREAM), %o3 ! assume %hi(MXCC_SRCSTREAM) == %hi(MXCC_DESTSTREAM)
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mov 0x10, %g2 ! set cacheable bit
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or %o3, %lo(MXCC_SRCSTREAM), %o2
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or %o3, %lo(MXCC_DESSTREAM), %o3
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sub %g3, MXCC_STREAM_SIZE, %g3
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6:
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stda %g2, [%o2] ASI_M_MXCC
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stda %g2, [%o3] ASI_M_MXCC
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andncc %g3, PAGE_MASK, %g0
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bne 6b
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sub %g3, MXCC_STREAM_SIZE, %g3
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9: retl
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nop
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viking_flush_cache_page:
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viking_flush_cache_range:
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#ifndef CONFIG_SMP
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ld [%o0 + VMA_VM_MM], %o0
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#endif
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viking_flush_cache_mm:
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#ifndef CONFIG_SMP
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ld [%o0 + AOFF_mm_context], %g1
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cmp %g1, -1
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bne viking_flush_cache_all
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nop
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b,a viking_flush_cache_out
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#endif
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viking_flush_cache_all:
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WINDOW_FLUSH(%g4, %g5)
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viking_flush_cache_out:
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retl
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nop
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viking_flush_tlb_all:
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mov 0x400, %g1
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retl
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sta %g0, [%g1] ASI_M_FLUSH_PROBE
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viking_flush_tlb_mm:
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o1
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lda [%g1] ASI_M_MMUREGS, %g5
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#ifndef CONFIG_SMP
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cmp %o1, -1
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be 1f
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#endif
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mov 0x300, %g2
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sta %o1, [%g1] ASI_M_MMUREGS
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sta %g0, [%g2] ASI_M_FLUSH_PROBE
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retl
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sta %g5, [%g1] ASI_M_MMUREGS
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#ifndef CONFIG_SMP
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1: retl
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nop
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#endif
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viking_flush_tlb_range:
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ld [%o0 + VMA_VM_MM], %o0
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o3
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lda [%g1] ASI_M_MMUREGS, %g5
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#ifndef CONFIG_SMP
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cmp %o3, -1
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be 2f
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#endif
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sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
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sta %o3, [%g1] ASI_M_MMUREGS
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and %o1, %o4, %o1
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add %o1, 0x200, %o1
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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1: sub %o1, %o4, %o1
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cmp %o1, %o2
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blu,a 1b
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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retl
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sta %g5, [%g1] ASI_M_MMUREGS
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#ifndef CONFIG_SMP
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2: retl
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nop
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#endif
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viking_flush_tlb_page:
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ld [%o0 + VMA_VM_MM], %o0
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o3
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lda [%g1] ASI_M_MMUREGS, %g5
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#ifndef CONFIG_SMP
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cmp %o3, -1
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be 1f
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#endif
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and %o1, PAGE_MASK, %o1
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sta %o3, [%g1] ASI_M_MMUREGS
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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retl
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sta %g5, [%g1] ASI_M_MMUREGS
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#ifndef CONFIG_SMP
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1: retl
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nop
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#endif
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viking_flush_page_to_ram:
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viking_flush_page_for_dma:
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viking_flush_sig_insns:
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retl
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nop
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#ifdef CONFIG_SMP
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.globl sun4dsmp_flush_tlb_all, sun4dsmp_flush_tlb_mm
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.globl sun4dsmp_flush_tlb_range, sun4dsmp_flush_tlb_page
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sun4dsmp_flush_tlb_all:
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sethi %hi(sun4dsmp_flush_tlb_spin), %g3
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1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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tst %g5
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bne 2f
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mov 0x400, %g1
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sta %g0, [%g1] ASI_M_FLUSH_PROBE
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retl
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stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
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2: tst %g5
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bne,a 2b
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ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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b,a 1b
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sun4dsmp_flush_tlb_mm:
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sethi %hi(sun4dsmp_flush_tlb_spin), %g3
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1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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tst %g5
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bne 2f
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + AOFF_mm_context], %o1
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lda [%g1] ASI_M_MMUREGS, %g5
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mov 0x300, %g2
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sta %o1, [%g1] ASI_M_MMUREGS
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sta %g0, [%g2] ASI_M_FLUSH_PROBE
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sta %g5, [%g1] ASI_M_MMUREGS
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retl
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stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
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2: tst %g5
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bne,a 2b
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ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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b,a 1b
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sun4dsmp_flush_tlb_range:
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sethi %hi(sun4dsmp_flush_tlb_spin), %g3
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1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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tst %g5
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bne 3f
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + VMA_VM_MM], %o0
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ld [%o0 + AOFF_mm_context], %o3
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lda [%g1] ASI_M_MMUREGS, %g5
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sethi %hi(~((1 << PGDIR_SHIFT) - 1)), %o4
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sta %o3, [%g1] ASI_M_MMUREGS
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and %o1, %o4, %o1
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add %o1, 0x200, %o1
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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2: sub %o1, %o4, %o1
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cmp %o1, %o2
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blu,a 2b
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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sta %g5, [%g1] ASI_M_MMUREGS
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retl
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stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
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3: tst %g5
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bne,a 3b
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ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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b,a 1b
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sun4dsmp_flush_tlb_page:
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sethi %hi(sun4dsmp_flush_tlb_spin), %g3
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1: ldstub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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tst %g5
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bne 2f
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mov SRMMU_CTX_REG, %g1
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ld [%o0 + VMA_VM_MM], %o0
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ld [%o0 + AOFF_mm_context], %o3
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lda [%g1] ASI_M_MMUREGS, %g5
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and %o1, PAGE_MASK, %o1
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sta %o3, [%g1] ASI_M_MMUREGS
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sta %g0, [%o1] ASI_M_FLUSH_PROBE
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sta %g5, [%g1] ASI_M_MMUREGS
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retl
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stb %g0, [%g3 + %lo(sun4dsmp_flush_tlb_spin)]
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2: tst %g5
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bne,a 2b
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ldub [%g3 + %lo(sun4dsmp_flush_tlb_spin)], %g5
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b,a 1b
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nop
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#endif
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