forked from luck/tmp_suning_uos_patched
1e61405e20
ADC and DAC can be clocked from separate or same sources CLK1 and CLK2. By default, ADC is clocked from CLK1, and DAC - from CLK2. This commits allows sound cards to selest a proper clock source during `hw_params()` via `snd_soc_dai_set_sysclk()`. It makes possible to have a single clock source for both ADC and DAC. Signed-off-by: Kirill Marinushkin <kmarinushkin@birdec.tech> Signed-off-by: Mark Brown <broonie@kernel.org>
97 lines
2.4 KiB
C
97 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PCM3060 codec driver
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*
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* Copyright (C) 2018 Kirill Marinushkin <kmarinushkin@birdec.tech>
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*/
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#ifndef _SND_SOC_PCM3060_H
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#define _SND_SOC_PCM3060_H
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#include <linux/device.h>
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#include <linux/regmap.h>
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extern const struct regmap_config pcm3060_regmap;
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#define PCM3060_DAI_ID_DAC 0
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#define PCM3060_DAI_ID_ADC 1
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#define PCM3060_DAI_IDS_NUM 2
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/* ADC and DAC can be clocked from separate or same sources CLK1 and CLK2 */
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#define PCM3060_CLK_DEF 0 /* default: CLK1->ADC, CLK2->DAC */
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#define PCM3060_CLK1 1
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#define PCM3060_CLK2 2
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struct pcm3060_priv_dai {
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bool is_master;
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unsigned int sclk_freq;
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};
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struct pcm3060_priv {
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struct regmap *regmap;
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struct pcm3060_priv_dai dai[PCM3060_DAI_IDS_NUM];
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u8 out_se: 1;
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};
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int pcm3060_probe(struct device *dev);
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int pcm3060_remove(struct device *dev);
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/* registers */
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#define PCM3060_REG64 0x40
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#define PCM3060_REG_MRST 0x80
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#define PCM3060_REG_SRST 0x40
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#define PCM3060_REG_ADPSV 0x20
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#define PCM3060_REG_SHIFT_ADPSV 0x05
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#define PCM3060_REG_DAPSV 0x10
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#define PCM3060_REG_SHIFT_DAPSV 0x04
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#define PCM3060_REG_SE 0x01
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#define PCM3060_REG65 0x41
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#define PCM3060_REG66 0x42
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#define PCM3060_REG_AT2_MIN 0x36
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#define PCM3060_REG_AT2_MAX 0xFF
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#define PCM3060_REG67 0x43
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#define PCM3060_REG72 0x48
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#define PCM3060_REG_CSEL 0x80
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#define PCM3060_REG_MASK_MS 0x70
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#define PCM3060_REG_MS_S 0x00
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#define PCM3060_REG_MS_M768 (0x01 << 4)
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#define PCM3060_REG_MS_M512 (0x02 << 4)
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#define PCM3060_REG_MS_M384 (0x03 << 4)
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#define PCM3060_REG_MS_M256 (0x04 << 4)
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#define PCM3060_REG_MS_M192 (0x05 << 4)
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#define PCM3060_REG_MS_M128 (0x06 << 4)
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#define PCM3060_REG_MASK_FMT 0x03
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#define PCM3060_REG_FMT_I2S 0x00
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#define PCM3060_REG_FMT_LJ 0x01
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#define PCM3060_REG_FMT_RJ 0x02
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#define PCM3060_REG68 0x44
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#define PCM3060_REG_OVER 0x40
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#define PCM3060_REG_DREV2 0x04
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#define PCM3060_REG_SHIFT_MUT21 0x00
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#define PCM3060_REG_SHIFT_MUT22 0x01
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#define PCM3060_REG69 0x45
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#define PCM3060_REG_FLT 0x80
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#define PCM3060_REG_MASK_DMF 0x60
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#define PCM3060_REG_DMC 0x10
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#define PCM3060_REG_ZREV 0x02
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#define PCM3060_REG_AZRO 0x01
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#define PCM3060_REG70 0x46
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#define PCM3060_REG71 0x47
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#define PCM3060_REG_AT1_MIN 0x0E
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#define PCM3060_REG_AT1_MAX 0xFF
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#define PCM3060_REG73 0x49
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#define PCM3060_REG_ZCDD 0x10
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#define PCM3060_REG_BYP 0x08
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#define PCM3060_REG_DREV1 0x04
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#define PCM3060_REG_SHIFT_MUT11 0x00
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#define PCM3060_REG_SHIFT_MUT12 0x01
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#endif /* _SND_SOC_PCM3060_H */
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