forked from luck/tmp_suning_uos_patched
1fc711f7ff
In kexec_prepare_cpus, the primary CPU IPIs the secondary CPUs to kexec_smp_down(). kexec_smp_down() calls kexec_smp_wait() which sets the hw_cpu_id() to -1. The primary does this while leaving IRQs on which means the primary can take a timer interrupt which can lead to the IPIing one of the secondary CPUs (say, for a scheduler re-balance) but since the secondary CPU now has a hw_cpu_id = -1, we IPI CPU -1... Kaboom! We are hitting this case regularly on POWER7 machines. There is also a second race, where the primary will tear down the MMU mappings before knowing the secondaries have entered real mode. Also, the secondaries are clearing out any pending IPIs before guaranteeing that no more will be received. This changes kexec_prepare_cpus() so that we turn off IRQs in the primary CPU much earlier. It adds a paca flag to say that the secondaries have entered the kexec_smp_down() IPI and turned off IRQs, rather than overloading hw_cpu_id with -1. This new paca flag is again used to in indicate when the secondaries has entered real mode. It also ensures that all CPUs have their IRQs off before we clear out any pending IPI requests (in kexec_cpu_down()) to ensure there are no trailing IPIs left unacknowledged. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
158 lines
4.6 KiB
C
158 lines
4.6 KiB
C
/*
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* c 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <linux/module.h>
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#include <linux/lmb.h>
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#include <asm/firmware.h>
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#include <asm/lppaca.h>
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#include <asm/paca.h>
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#include <asm/sections.h>
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#include <asm/pgtable.h>
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#include <asm/iseries/lpar_map.h>
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#include <asm/iseries/hv_types.h>
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#include <asm/kexec.h>
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/* This symbol is provided by the linker - let it fill in the paca
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* field correctly */
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extern unsigned long __toc_start;
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#ifdef CONFIG_PPC_BOOK3S
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/*
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* The structure which the hypervisor knows about - this structure
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* should not cross a page boundary. The vpa_init/register_vpa call
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* is now known to fail if the lppaca structure crosses a page
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* boundary. The lppaca is also used on legacy iSeries and POWER5
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* pSeries boxes. The lppaca is 640 bytes long, and cannot readily
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* change since the hypervisor knows its layout, so a 1kB alignment
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* will suffice to ensure that it doesn't cross a page boundary.
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*/
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struct lppaca lppaca[] = {
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[0 ... (NR_CPUS-1)] = {
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.desc = 0xd397d781, /* "LpPa" */
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.size = sizeof(struct lppaca),
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.dyn_proc_status = 2,
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.decr_val = 0x00ff0000,
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.fpregs_in_use = 1,
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.end_of_quantum = 0xfffffffffffffffful,
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.slb_count = 64,
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.vmxregs_in_use = 0,
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.page_ins = 0,
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},
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};
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#endif /* CONFIG_PPC_BOOK3S */
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#ifdef CONFIG_PPC_STD_MMU_64
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/*
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* 3 persistent SLBs are registered here. The buffer will be zero
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* initially, hence will all be invaild until we actually write them.
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*/
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struct slb_shadow slb_shadow[] __cacheline_aligned = {
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[0 ... (NR_CPUS-1)] = {
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.persistent = SLB_NUM_BOLTED,
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.buffer_length = sizeof(struct slb_shadow),
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},
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};
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#endif /* CONFIG_PPC_STD_MMU_64 */
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/* The Paca is an array with one entry per processor. Each contains an
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* lppaca, which contains the information shared between the
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* hypervisor and Linux.
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* On systems with hardware multi-threading, there are two threads
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* per processor. The Paca array must contain an entry for each thread.
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* The VPD Areas will give a max logical processors = 2 * max physical
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* processors. The processor VPD array needs one entry per physical
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* processor (not thread).
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*/
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struct paca_struct *paca;
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EXPORT_SYMBOL(paca);
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struct paca_struct boot_paca;
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void __init initialise_paca(struct paca_struct *new_paca, int cpu)
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{
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/* The TOC register (GPR2) points 32kB into the TOC, so that 64kB
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* of the TOC can be addressed using a single machine instruction.
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*/
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unsigned long kernel_toc = (unsigned long)(&__toc_start) + 0x8000UL;
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#ifdef CONFIG_PPC_BOOK3S
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new_paca->lppaca_ptr = &lppaca[cpu];
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#else
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new_paca->kernel_pgd = swapper_pg_dir;
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#endif
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new_paca->lock_token = 0x8000;
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new_paca->paca_index = cpu;
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new_paca->kernel_toc = kernel_toc;
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new_paca->kernelbase = (unsigned long) _stext;
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new_paca->kernel_msr = MSR_KERNEL;
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new_paca->hw_cpu_id = 0xffff;
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new_paca->kexec_state = KEXEC_STATE_NONE;
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new_paca->__current = &init_task;
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#ifdef CONFIG_PPC_STD_MMU_64
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new_paca->slb_shadow_ptr = &slb_shadow[cpu];
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#endif /* CONFIG_PPC_STD_MMU_64 */
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}
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static int __initdata paca_size;
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void __init allocate_pacas(void)
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{
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int nr_cpus, cpu, limit;
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/*
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* We can't take SLB misses on the paca, and we want to access them
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* in real mode, so allocate them within the RMA and also within
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* the first segment. On iSeries they must be within the area mapped
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* by the HV, which is HvPagesToMap * HVPAGESIZE bytes.
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*/
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limit = min(0x10000000ULL, lmb.rmo_size);
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if (firmware_has_feature(FW_FEATURE_ISERIES))
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limit = min(limit, HvPagesToMap * HVPAGESIZE);
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nr_cpus = NR_CPUS;
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/* On iSeries we know we can never have more than 64 cpus */
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if (firmware_has_feature(FW_FEATURE_ISERIES))
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nr_cpus = min(64, nr_cpus);
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paca_size = PAGE_ALIGN(sizeof(struct paca_struct) * nr_cpus);
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paca = __va(lmb_alloc_base(paca_size, PAGE_SIZE, limit));
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memset(paca, 0, paca_size);
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printk(KERN_DEBUG "Allocated %u bytes for %d pacas at %p\n",
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paca_size, nr_cpus, paca);
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/* Can't use for_each_*_cpu, as they aren't functional yet */
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for (cpu = 0; cpu < nr_cpus; cpu++)
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initialise_paca(&paca[cpu], cpu);
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}
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void __init free_unused_pacas(void)
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{
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int new_size;
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new_size = PAGE_ALIGN(sizeof(struct paca_struct) * num_possible_cpus());
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if (new_size >= paca_size)
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return;
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lmb_free(__pa(paca) + new_size, paca_size - new_size);
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printk(KERN_DEBUG "Freed %u bytes for unused pacas\n",
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paca_size - new_size);
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paca_size = new_size;
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}
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