forked from luck/tmp_suning_uos_patched
08687aec71
This is the last unification step. Here we do remove one of the files and rename the left one as cpu.c, as both are now the same. Also update power/Makefile, telling it to build cpu.o, instead of cpu_(32|64).o Signed-off-by: Sergio Luis <sergio@larces.uece.br> Signed-off-by: Lauro Salmito <laurosalmito@gmail.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
260 lines
6.2 KiB
C
260 lines
6.2 KiB
C
/*
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* Suspend support specific for i386/x86-64.
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*
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* Distribute under GPLv2
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*
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* Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
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* Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
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* Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
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*/
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#include <linux/suspend.h>
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#include <linux/smp.h>
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#include <asm/pgtable.h>
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#include <asm/proto.h>
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#include <asm/mtrr.h>
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#include <asm/page.h>
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#include <asm/mce.h>
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#include <asm/xcr.h>
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#include <asm/suspend.h>
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#ifdef CONFIG_X86_32
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static struct saved_context saved_context;
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unsigned long saved_context_ebx;
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unsigned long saved_context_esp, saved_context_ebp;
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unsigned long saved_context_esi, saved_context_edi;
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unsigned long saved_context_eflags;
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#else
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/* CONFIG_X86_64 */
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struct saved_context saved_context;
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#endif
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/**
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* __save_processor_state - save CPU registers before creating a
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* hibernation image and before restoring the memory state from it
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* @ctxt - structure to store the registers contents in
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*
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* NOTE: If there is a CPU register the modification of which by the
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* boot kernel (ie. the kernel used for loading the hibernation image)
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* might affect the operations of the restored target kernel (ie. the one
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* saved in the hibernation image), then its contents must be saved by this
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* function. In other words, if kernel A is hibernated and different
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* kernel B is used for loading the hibernation image into memory, the
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* kernel A's __save_processor_state() function must save all registers
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* needed by kernel A, so that it can operate correctly after the resume
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* regardless of what kernel B does in the meantime.
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*/
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static void __save_processor_state(struct saved_context *ctxt)
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{
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#ifdef CONFIG_X86_32
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mtrr_save_fixed_ranges(NULL);
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#endif
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kernel_fpu_begin();
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/*
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* descriptor tables
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*/
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#ifdef CONFIG_X86_32
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store_gdt(&ctxt->gdt);
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store_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
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store_idt((struct desc_ptr *)&ctxt->idt_limit);
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#endif
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store_tr(ctxt->tr);
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/* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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savesegment(es, ctxt->es);
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savesegment(fs, ctxt->fs);
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savesegment(gs, ctxt->gs);
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savesegment(ss, ctxt->ss);
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
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asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
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asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
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asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
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asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
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rdmsrl(MSR_FS_BASE, ctxt->fs_base);
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rdmsrl(MSR_GS_BASE, ctxt->gs_base);
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rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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mtrr_save_fixed_ranges(NULL);
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rdmsrl(MSR_EFER, ctxt->efer);
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#endif
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/*
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* control registers
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*/
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ctxt->cr0 = read_cr0();
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ctxt->cr2 = read_cr2();
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ctxt->cr3 = read_cr3();
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#ifdef CONFIG_X86_32
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ctxt->cr4 = read_cr4_safe();
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#else
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/* CONFIG_X86_64 */
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ctxt->cr4 = read_cr4();
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ctxt->cr8 = read_cr8();
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#endif
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}
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/* Needed by apm.c */
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void save_processor_state(void)
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{
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__save_processor_state(&saved_context);
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(save_processor_state);
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#endif
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static void do_fpu_end(void)
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{
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/*
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* Restore FPU regs if necessary.
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*/
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kernel_fpu_end();
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}
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static void fix_processor_context(void)
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{
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int cpu = smp_processor_id();
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struct tss_struct *t = &per_cpu(init_tss, cpu);
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set_tss_desc(cpu, t); /*
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* This just modifies memory; should not be
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* necessary. But... This is necessary, because
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* 386 hardware has concept of busy TSS or some
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* similar stupidity.
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*/
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#ifdef CONFIG_X86_64
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get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
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syscall_init(); /* This sets MSR_*STAR and related */
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#endif
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load_TR_desc(); /* This does ltr */
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load_LDT(¤t->active_mm->context); /* This does lldt */
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/*
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* Now maybe reload the debug registers
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*/
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if (current->thread.debugreg7) {
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#ifdef CONFIG_X86_32
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set_debugreg(current->thread.debugreg0, 0);
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set_debugreg(current->thread.debugreg1, 1);
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set_debugreg(current->thread.debugreg2, 2);
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set_debugreg(current->thread.debugreg3, 3);
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/* no 4 and 5 */
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set_debugreg(current->thread.debugreg6, 6);
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set_debugreg(current->thread.debugreg7, 7);
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#else
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/* CONFIG_X86_64 */
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loaddebug(¤t->thread, 0);
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loaddebug(¤t->thread, 1);
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loaddebug(¤t->thread, 2);
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loaddebug(¤t->thread, 3);
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/* no 4 and 5 */
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loaddebug(¤t->thread, 6);
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loaddebug(¤t->thread, 7);
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#endif
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}
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}
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/**
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* __restore_processor_state - restore the contents of CPU registers saved
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* by __save_processor_state()
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* @ctxt - structure to load the registers contents from
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*/
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static void __restore_processor_state(struct saved_context *ctxt)
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{
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/*
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* control registers
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*/
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/* cr4 was introduced in the Pentium CPU */
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#ifdef CONFIG_X86_32
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if (ctxt->cr4)
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write_cr4(ctxt->cr4);
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#else
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/* CONFIG X86_64 */
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wrmsrl(MSR_EFER, ctxt->efer);
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write_cr8(ctxt->cr8);
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write_cr4(ctxt->cr4);
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#endif
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write_cr3(ctxt->cr3);
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write_cr2(ctxt->cr2);
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write_cr0(ctxt->cr0);
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/*
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* now restore the descriptor tables to their proper values
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* ltr is done i fix_processor_context().
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*/
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#ifdef CONFIG_X86_32
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load_gdt(&ctxt->gdt);
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load_idt(&ctxt->idt);
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#else
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/* CONFIG_X86_64 */
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load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
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load_idt((const struct desc_ptr *)&ctxt->idt_limit);
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#endif
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/*
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* segment registers
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*/
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#ifdef CONFIG_X86_32
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loadsegment(es, ctxt->es);
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loadsegment(fs, ctxt->fs);
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loadsegment(gs, ctxt->gs);
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loadsegment(ss, ctxt->ss);
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/*
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* sysenter MSRs
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*/
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if (boot_cpu_has(X86_FEATURE_SEP))
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enable_sep_cpu();
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#else
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/* CONFIG_X86_64 */
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asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
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asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
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asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
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load_gs_index(ctxt->gs);
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asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
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wrmsrl(MSR_FS_BASE, ctxt->fs_base);
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wrmsrl(MSR_GS_BASE, ctxt->gs_base);
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wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
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#endif
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/*
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* restore XCR0 for xsave capable cpu's.
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*/
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if (cpu_has_xsave)
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xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
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fix_processor_context();
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do_fpu_end();
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mtrr_ap_init();
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#ifdef CONFIG_X86_32
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mcheck_init(&boot_cpu_data);
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#endif
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}
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/* Needed by apm.c */
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void restore_processor_state(void)
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{
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__restore_processor_state(&saved_context);
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}
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#ifdef CONFIG_X86_32
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EXPORT_SYMBOL(restore_processor_state);
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#endif
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