forked from luck/tmp_suning_uos_patched
b2b3631662
Commit d2c3706842 ([ARM] pxa:
initialize default interrupt priority and use ICHP for IRQ handling)
broke ISA interrupt support on pxa27x/3xx.
In such a case, PXA_IRQ(0) != 0, and the IRQ number computed from
ICHP must be offset by PXA_IRQ(0).
Tested on an Arcom Zeus (pxa270), with both CONFIG_PXA_HAVE_ISA_IRQS
enabled and disabled.
Signed-off-by: Marc Zyngier <maz@misterjones.org>
Tested-by: Haojian Zhuang <haojian.zhuang@marvell.com>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
52 lines
1.3 KiB
ArmAsm
52 lines
1.3 KiB
ArmAsm
/*
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* arch/arm/mach-pxa/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for PXA-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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.macro disable_fiq
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.endm
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
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mov \tmp, \tmp, lsr #13
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and \tmp, \tmp, #0x7 @ Core G
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cmp \tmp, #1
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bhi 1002f
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@ Core Generation 1 (PXA25x)
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mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
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add \base, \base, #0x00d00000
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ldr \irqstat, [\base, #0] @ ICIP
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ldr \irqnr, [\base, #4] @ ICMR
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ands \irqnr, \irqstat, \irqnr
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beq 1001f
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rsb \irqstat, \irqnr, #0
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and \irqstat, \irqstat, \irqnr
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clz \irqnr, \irqstat
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rsb \irqnr, \irqnr, #(31 + PXA_IRQ(0))
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b 1001f
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1002:
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@ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
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mrc p6, 0, \irqstat, c5, c0, 0 @ ICHP
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tst \irqstat, #0x80000000
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beq 1001f
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bic \irqstat, \irqstat, #0x80000000
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mov \irqnr, \irqstat, lsr #16
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add \irqnr, \irqnr, #(PXA_IRQ(0))
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1001:
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.endm
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