forked from luck/tmp_suning_uos_patched
7379e65279
The zcrypt device driver does not handle CPRBs which address
a control domain correctly. This fix introduces a workaround:
The domain field of the request CPRB is checked if there is
a valid domain value in there. If this is true and the value
is a control only domain (a domain which is enabled in the
crypto config ADM mask but disabled in the AQM mask) the
CPRB is forwarded to the default usage domain. If there is
no default domain, the request is rejected with an ENODEV.
This fix is important for maintaining crypto adapters. For
example one LPAR can use a crypto adapter domain ('Control
and Usage') but another LPAR needs to be able to maintain
this adapter domain ('Control'). Scenarios like this did
not work properly and the patch enables this.
Signed-off-by: Harald Freudenberger <freude@linux.ibm.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
375 lines
10 KiB
C
375 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Adjunct processor (AP) interfaces
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*
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* Copyright IBM Corp. 2017
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*
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* Author(s): Tony Krowiak <akrowia@linux.vnet.ibm.com>
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* Martin Schwidefsky <schwidefsky@de.ibm.com>
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* Harald Freudenberger <freude@de.ibm.com>
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*/
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#ifndef _ASM_S390_AP_H_
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#define _ASM_S390_AP_H_
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/**
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* The ap_qid_t identifier of an ap queue.
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* If the AP facilities test (APFT) facility is available,
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* card and queue index are 8 bit values, otherwise
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* card index is 6 bit and queue index a 4 bit value.
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*/
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typedef unsigned int ap_qid_t;
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#define AP_MKQID(_card, _queue) (((_card) & 0xff) << 8 | ((_queue) & 0xff))
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#define AP_QID_CARD(_qid) (((_qid) >> 8) & 0xff)
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#define AP_QID_QUEUE(_qid) ((_qid) & 0xff)
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/**
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* struct ap_queue_status - Holds the AP queue status.
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* @queue_empty: Shows if queue is empty
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* @replies_waiting: Waiting replies
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* @queue_full: Is 1 if the queue is full
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* @irq_enabled: Shows if interrupts are enabled for the AP
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* @response_code: Holds the 8 bit response code
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*
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* The ap queue status word is returned by all three AP functions
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* (PQAP, NQAP and DQAP). There's a set of flags in the first
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* byte, followed by a 1 byte response code.
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*/
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struct ap_queue_status {
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unsigned int queue_empty : 1;
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unsigned int replies_waiting : 1;
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unsigned int queue_full : 1;
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unsigned int _pad1 : 4;
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unsigned int irq_enabled : 1;
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unsigned int response_code : 8;
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unsigned int _pad2 : 16;
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};
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/**
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* ap_intructions_available() - Test if AP instructions are available.
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*
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* Returns true if the AP instructions are installed, otherwise false.
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*/
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static inline bool ap_instructions_available(void)
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{
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register unsigned long reg0 asm ("0") = AP_MKQID(0, 0);
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register unsigned long reg1 asm ("1") = 0;
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register unsigned long reg2 asm ("2") = 0;
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asm volatile(
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" .long 0xb2af0000\n" /* PQAP(TAPQ) */
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"0: la %0,1\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg1), "+d" (reg2)
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: "d" (reg0)
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: "cc");
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return reg1 != 0;
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}
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/**
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* ap_tapq(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_tapq(ap_qid_t qid, unsigned long *info)
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{
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register unsigned long reg0 asm ("0") = qid;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2");
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asm volatile(".long 0xb2af0000" /* PQAP(TAPQ) */
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: "=d" (reg1), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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if (info)
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*info = reg2;
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return reg1;
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}
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/**
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* ap_test_queue(): Test adjunct processor queue.
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* @qid: The AP queue number
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* @tbit: Test facilities bit
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* @info: Pointer to queue descriptor
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_test_queue(ap_qid_t qid,
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int tbit,
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unsigned long *info)
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{
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if (tbit)
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qid |= 1UL << 23; /* set T bit*/
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return ap_tapq(qid, info);
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}
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/**
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* ap_pqap_rapq(): Reset adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_rapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | (1UL << 24);
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register struct ap_queue_status reg1 asm ("1");
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asm volatile(
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".long 0xb2af0000" /* PQAP(RAPQ) */
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: "=d" (reg1)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* ap_pqap_zapq(): Reset and zeroize adjunct processor queue.
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* @qid: The AP queue number
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*
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* Returns AP queue status structure.
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*/
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static inline struct ap_queue_status ap_zapq(ap_qid_t qid)
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{
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register unsigned long reg0 asm ("0") = qid | (2UL << 24);
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register struct ap_queue_status reg1 asm ("1");
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asm volatile(
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".long 0xb2af0000" /* PQAP(ZAPQ) */
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: "=d" (reg1)
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: "d" (reg0)
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: "cc");
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return reg1;
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}
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/**
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* struct ap_config_info - convenience struct for AP crypto
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* config info as returned by the ap_qci() function.
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*/
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struct ap_config_info {
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unsigned int apsc : 1; /* S bit */
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unsigned int apxa : 1; /* N bit */
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unsigned int qact : 1; /* C bit */
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unsigned int rc8a : 1; /* R bit */
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unsigned char _reserved1 : 4;
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unsigned char _reserved2[3];
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unsigned char Na; /* max # of APs - 1 */
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unsigned char Nd; /* max # of Domains - 1 */
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unsigned char _reserved3[10];
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unsigned int apm[8]; /* AP ID mask */
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unsigned int aqm[8]; /* AP (usage) queue mask */
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unsigned int adm[8]; /* AP (control) domain mask */
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unsigned char _reserved4[16];
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} __aligned(8);
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/**
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* ap_qci(): Get AP configuration data
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*
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* Returns 0 on success, or -EOPNOTSUPP.
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*/
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static inline int ap_qci(struct ap_config_info *config)
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{
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register unsigned long reg0 asm ("0") = 4UL << 24;
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register unsigned long reg1 asm ("1") = -EOPNOTSUPP;
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register struct ap_config_info *reg2 asm ("2") = config;
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asm volatile(
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".long 0xb2af0000\n" /* PQAP(QCI) */
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"0: la %0,0\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: "+d" (reg1)
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: "d" (reg0), "d" (reg2)
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: "cc", "memory");
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return reg1;
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}
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/*
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* struct ap_qirq_ctrl - convenient struct for easy invocation
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* of the ap_aqic() function. This struct is passed as GR1
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* parameter to the PQAP(AQIC) instruction. For details please
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* see the AR documentation.
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*/
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struct ap_qirq_ctrl {
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unsigned int _res1 : 8;
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unsigned int zone : 8; /* zone info */
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unsigned int ir : 1; /* ir flag: enable (1) or disable (0) irq */
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unsigned int _res2 : 4;
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unsigned int gisc : 3; /* guest isc field */
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unsigned int _res3 : 6;
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unsigned int gf : 2; /* gisa format */
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unsigned int _res4 : 1;
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unsigned int gisa : 27; /* gisa origin */
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unsigned int _res5 : 1;
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unsigned int isc : 3; /* irq sub class */
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};
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/**
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* ap_aqic(): Control interruption for a specific AP.
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* @qid: The AP queue number
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* @qirqctrl: struct ap_qirq_ctrl (64 bit value)
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* @ind: The notification indicator byte
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*
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* Returns AP queue status.
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*/
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static inline struct ap_queue_status ap_aqic(ap_qid_t qid,
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struct ap_qirq_ctrl qirqctrl,
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void *ind)
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{
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register unsigned long reg0 asm ("0") = qid | (3UL << 24);
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register union {
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unsigned long value;
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struct ap_qirq_ctrl qirqctrl;
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struct ap_queue_status status;
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} reg1 asm ("1");
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register void *reg2 asm ("2") = ind;
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reg1.qirqctrl = qirqctrl;
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asm volatile(
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".long 0xb2af0000" /* PQAP(AQIC) */
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: "+d" (reg1)
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: "d" (reg0), "d" (reg2)
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: "cc");
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return reg1.status;
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}
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/*
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* union ap_qact_ap_info - used together with the
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* ap_aqic() function to provide a convenient way
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* to handle the ap info needed by the qact function.
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*/
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union ap_qact_ap_info {
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unsigned long val;
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struct {
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unsigned int : 3;
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unsigned int mode : 3;
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unsigned int : 26;
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unsigned int cat : 8;
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unsigned int : 8;
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unsigned char ver[2];
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};
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};
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/**
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* ap_qact(): Query AP combatibility type.
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* @qid: The AP queue number
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* @apinfo: On input the info about the AP queue. On output the
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* alternate AP queue info provided by the qact function
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* in GR2 is stored in.
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*
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* Returns AP queue status. Check response_code field for failures.
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*/
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static inline struct ap_queue_status ap_qact(ap_qid_t qid, int ifbit,
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union ap_qact_ap_info *apinfo)
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{
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register unsigned long reg0 asm ("0") = qid | (5UL << 24)
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| ((ifbit & 0x01) << 22);
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register union {
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unsigned long value;
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struct ap_queue_status status;
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} reg1 asm ("1");
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register unsigned long reg2 asm ("2");
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reg1.value = apinfo->val;
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asm volatile(
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".long 0xb2af0000" /* PQAP(QACT) */
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: "+d" (reg1), "=d" (reg2)
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: "d" (reg0)
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: "cc");
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apinfo->val = reg2;
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return reg1.status;
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}
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/**
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* ap_nqap(): Send message to adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: The program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on NQAP can't happen because the L bit is 1.
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* Condition code 2 on NQAP also means the send is incomplete,
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* because a segment boundary was reached. The NQAP is repeated.
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*/
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static inline struct ap_queue_status ap_nqap(ap_qid_t qid,
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unsigned long long psmid,
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void *msg, size_t length)
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{
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register unsigned long reg0 asm ("0") = qid | 0x40000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm ("2") = (unsigned long) msg;
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register unsigned long reg3 asm ("3") = (unsigned long) length;
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register unsigned long reg4 asm ("4") = (unsigned int) (psmid >> 32);
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register unsigned long reg5 asm ("5") = psmid & 0xffffffff;
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asm volatile (
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"0: .long 0xb2ad0042\n" /* NQAP */
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" brc 2,0b"
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: "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3)
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: "d" (reg4), "d" (reg5)
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: "cc", "memory");
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return reg1;
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}
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/**
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* ap_dqap(): Receive message from adjunct processor queue.
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* @qid: The AP queue number
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* @psmid: Pointer to program supplied message identifier
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* @msg: The message text
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* @length: The message length
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*
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* Returns AP queue status structure.
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* Condition code 1 on DQAP means the receive has taken place
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* but only partially. The response is incomplete, hence the
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* DQAP is repeated.
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* Condition code 2 on DQAP also means the receive is incomplete,
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* this time because a segment boundary was reached. Again, the
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* DQAP is repeated.
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* Note that gpr2 is used by the DQAP instruction to keep track of
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* any 'residual' length, in case the instruction gets interrupted.
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* Hence it gets zeroed before the instruction.
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*/
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static inline struct ap_queue_status ap_dqap(ap_qid_t qid,
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unsigned long long *psmid,
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void *msg, size_t length)
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{
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register unsigned long reg0 asm("0") = qid | 0x80000000UL;
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register struct ap_queue_status reg1 asm ("1");
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register unsigned long reg2 asm("2") = 0UL;
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register unsigned long reg4 asm("4") = (unsigned long) msg;
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register unsigned long reg5 asm("5") = (unsigned long) length;
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register unsigned long reg6 asm("6") = 0UL;
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register unsigned long reg7 asm("7") = 0UL;
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asm volatile(
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"0: .long 0xb2ae0064\n" /* DQAP */
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" brc 6,0b\n"
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: "+d" (reg0), "=d" (reg1), "+d" (reg2),
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"+d" (reg4), "+d" (reg5), "+d" (reg6), "+d" (reg7)
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: : "cc", "memory");
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*psmid = (((unsigned long long) reg6) << 32) + reg7;
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return reg1;
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}
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/*
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* Interface to tell the AP bus code that a configuration
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* change has happened. The bus code should at least do
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* an ap bus resource rescan.
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*/
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#if IS_ENABLED(CONFIG_ZCRYPT)
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void ap_bus_cfg_chg(void);
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#else
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static inline void ap_bus_cfg_chg(void){};
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#endif
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#endif /* _ASM_S390_AP_H_ */
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