forked from luck/tmp_suning_uos_patched
d25220d2f2
Include <asm/xor.h> into arch/s390/lib/xor.c to expose xor_block_xc declaration and avoid the following sparse warning: arch/s390/lib/xor.c:128:27: warning: symbol 'xor_block_xc' was not declared. Should it be static? Signed-off-by: Vasily Gorbik <gor@linux.ibm.com>
137 lines
2.9 KiB
C
137 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Optimized xor_block operation for RAID4/5
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*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#include <linux/types.h>
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#include <linux/export.h>
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#include <linux/raid/xor.h>
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#include <asm/xor.h>
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static void xor_xc_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3:\n"
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: : "d" (bytes), "a" (p1), "a" (p2)
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: "0", "1", "cc", "memory");
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}
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static void xor_xc_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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"3:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3)
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: : "0", "1", "cc", "memory");
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}
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static void xor_xc_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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{
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" xc 0(256,%1),0(%4)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" ex %0,12(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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" xc 0(1,%1),0(%4)\n"
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"3:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4)
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: : "0", "1", "cc", "memory");
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}
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static void xor_xc_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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{
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/* Get around a gcc oddity */
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register unsigned long *reg7 asm ("7") = p5;
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asm volatile(
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" larl 1,2f\n"
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" xc 0(256,%1),0(%4)\n"
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" xc 0(256,%1),0(%5)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" la %5,256(%5)\n"
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" brctg 0,0b\n"
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"1: ex %0,0(1)\n"
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" ex %0,6(1)\n"
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" ex %0,12(1)\n"
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" ex %0,18(1)\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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" xc 0(1,%1),0(%3)\n"
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" xc 0(1,%1),0(%4)\n"
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" xc 0(1,%1),0(%5)\n"
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"3:\n"
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: "+d" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4),
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"+a" (reg7)
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: : "0", "1", "cc", "memory");
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}
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struct xor_block_template xor_block_xc = {
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.name = "xc",
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.do_2 = xor_xc_2,
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.do_3 = xor_xc_3,
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.do_4 = xor_xc_4,
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.do_5 = xor_xc_5,
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};
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EXPORT_SYMBOL(xor_block_xc);
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