forked from luck/tmp_suning_uos_patched
d5fb82137b
Pull irq fixes from Thomas Gleixner: "This contains: - a series of fixes for interrupt drivers to prevent a potential race when installing a chained interrupt handler - a fix for cpumask pointer misuse - a fix for using the wrong interrupt number from struct irq_data - removal of unused code and outdated comments - a few new helper functions which allow us to cleanup the interrupt handling code further in 4.3 I decided against doing the cleanup at the end of this merge window and rather do the preparatory steps for 4.3, so we can run the final ABI change at the end of the 4.3 merge window with less risk" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (26 commits) ARM/LPC32xx: Use irq not hwirq for __irq_set_handler_locked() genirq: Implement irq_set_handler_locked()/irq_set_chip_handler_name_locked() genirq: Introduce helper irq_desc_get_irq() genirq: Remove irq_node() genirq: Clean up outdated comments related to include/linux/irqdesc.h mn10300: Fix incorrect use of irq_data->affinity MIPS/ralink: Fix race in installing chained IRQ handler MIPS/pci: Fix race in installing chained IRQ handler MIPS/ath25: Fix race in installing chained IRQ handler MIPS/ath25: Fix race in installing chained IRQ handler m68k/psc: Fix race in installing chained IRQ handler avr32/at32ap: Fix race in installing chained IRQ handler sh/intc: Fix race in installing chained IRQ handler sh/intc: Fix potential race in installing chained IRQ handler pinctrl/sun4i: Fix race in installing chained IRQ handler pinctrl/samsung: Fix race in installing chained IRQ handler pinctrl/samsung: Fix race in installing chained IRQ handler pinctrl/exynos: Fix race in installing chained IRQ handler pinctrl/st: Fix race in installing chained IRQ handler pinctrl/adi2: Fix race in installing chained IRQ handler ...
365 lines
9.4 KiB
C
365 lines
9.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
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* Copyright (C) 2006 FON Technology, SL.
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* Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
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* Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
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*/
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/*
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* Platform devices for Atheros AR2315 SoCs
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/bitops.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <asm/bootinfo.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <ath25_platform.h>
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#include "devices.h"
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#include "ar2315.h"
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#include "ar2315_regs.h"
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static void __iomem *ar2315_rst_base;
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static struct irq_domain *ar2315_misc_irq_domain;
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static inline u32 ar2315_rst_reg_read(u32 reg)
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{
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return __raw_readl(ar2315_rst_base + reg);
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}
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static inline void ar2315_rst_reg_write(u32 reg, u32 val)
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{
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__raw_writel(val, ar2315_rst_base + reg);
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}
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static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
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{
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u32 ret = ar2315_rst_reg_read(reg);
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ret &= ~mask;
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ret |= val;
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ar2315_rst_reg_write(reg, ret);
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}
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static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
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{
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ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
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ar2315_rst_reg_read(AR2315_AHB_ERR1);
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pr_emerg("AHB fatal error\n");
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machine_restart("AHB error"); /* Catastrophic failure */
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return IRQ_HANDLED;
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}
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static struct irqaction ar2315_ahb_err_interrupt = {
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.handler = ar2315_ahb_err_handler,
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.name = "ar2315-ahb-error",
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};
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static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
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ar2315_rst_reg_read(AR2315_IMR);
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unsigned nr, misc_irq = 0;
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if (pending) {
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struct irq_domain *domain = irq_desc_get_handler_data(desc);
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nr = __ffs(pending);
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misc_irq = irq_find_mapping(domain, nr);
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}
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if (misc_irq) {
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if (nr == AR2315_MISC_IRQ_GPIO)
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ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
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else if (nr == AR2315_MISC_IRQ_WATCHDOG)
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ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
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generic_handle_irq(misc_irq);
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} else {
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spurious_interrupt();
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}
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}
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static void ar2315_misc_irq_unmask(struct irq_data *d)
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{
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ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
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}
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static void ar2315_misc_irq_mask(struct irq_data *d)
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{
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ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
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}
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static struct irq_chip ar2315_misc_irq_chip = {
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.name = "ar2315-misc",
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.irq_unmask = ar2315_misc_irq_unmask,
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.irq_mask = ar2315_misc_irq_mask,
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};
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static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
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return 0;
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}
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static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
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.map = ar2315_misc_irq_map,
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};
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/*
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* Called when an interrupt is received, this function
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* determines exactly which interrupt it was, and it
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* invokes the appropriate handler.
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*
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* Implicitly, we also define interrupt priority by
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* choosing which to dispatch first.
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*/
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static void ar2315_irq_dispatch(void)
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{
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u32 pending = read_c0_status() & read_c0_cause();
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if (pending & CAUSEF_IP3)
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do_IRQ(AR2315_IRQ_WLAN0);
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#ifdef CONFIG_PCI_AR2315
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else if (pending & CAUSEF_IP5)
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do_IRQ(AR2315_IRQ_LCBUS_PCI);
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#endif
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else if (pending & CAUSEF_IP2)
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do_IRQ(AR2315_IRQ_MISC);
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else if (pending & CAUSEF_IP7)
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do_IRQ(ATH25_IRQ_CPU_CLOCK);
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else
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spurious_interrupt();
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}
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void __init ar2315_arch_init_irq(void)
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{
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struct irq_domain *domain;
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unsigned irq;
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ath25_irq_dispatch = ar2315_irq_dispatch;
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domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
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&ar2315_misc_irq_domain_ops, NULL);
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if (!domain)
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panic("Failed to add IRQ domain");
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irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
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setup_irq(irq, &ar2315_ahb_err_interrupt);
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irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
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ar2315_misc_irq_handler, domain);
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ar2315_misc_irq_domain = domain;
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}
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void __init ar2315_init_devices(void)
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{
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/* Find board configuration */
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ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
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ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
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}
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static void ar2315_restart(char *command)
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{
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void (*mips_reset_vec)(void) = (void *)0xbfc00000;
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local_irq_disable();
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/* try reset the system via reset control */
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ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
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/* Cold reset does not work on the AR2315/6, use the GPIO reset bits
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* a workaround. Give it some time to attempt a gpio based hardware
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* reset (atheros reference design workaround) */
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/* TODO: implement the GPIO reset workaround */
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/* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
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* workaround. Attempt to jump to the mips reset location -
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* the boot loader itself might be able to recover the system */
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mips_reset_vec();
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}
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/*
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* This table is indexed by bits 5..4 of the CLOCKCTL1 register
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* to determine the predevisor value.
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*/
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static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
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static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
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static unsigned __init ar2315_sys_clk(u32 clock_ctl)
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{
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unsigned int pllc_ctrl, cpu_div;
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unsigned int pllc_out, refdiv, fdiv, divby2;
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unsigned int clk_div;
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pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
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refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
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refdiv = clockctl1_predivide_table[refdiv];
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fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
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divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
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pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv;
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/* clkm input selected */
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switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
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case 0:
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case 1:
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clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
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clk_div = pllc_divide_table[clk_div];
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break;
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case 2:
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clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
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clk_div = pllc_divide_table[clk_div];
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break;
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default:
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pllc_out = 40000000;
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clk_div = 1;
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break;
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}
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cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
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cpu_div = cpu_div * 2 ?: 1;
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return pllc_out / (clk_div * cpu_div);
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}
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static inline unsigned ar2315_cpu_frequency(void)
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{
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return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
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}
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static inline unsigned ar2315_apb_frequency(void)
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{
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return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
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}
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void __init ar2315_plat_time_init(void)
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{
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mips_hpt_frequency = ar2315_cpu_frequency() / 2;
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}
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void __init ar2315_plat_mem_setup(void)
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{
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void __iomem *sdram_base;
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u32 memsize, memcfg;
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u32 devid;
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u32 config;
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/* Detect memory size */
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sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
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AR2315_SDRAMCTL_SIZE);
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memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
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memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
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memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
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memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
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memsize <<= 3;
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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iounmap(sdram_base);
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ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
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/* Detect the hardware based on the device ID */
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devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
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switch (devid) {
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case 0x91: /* Need to check */
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ath25_soc = ATH25_SOC_AR2318;
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break;
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case 0x90:
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ath25_soc = ATH25_SOC_AR2317;
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break;
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case 0x87:
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ath25_soc = ATH25_SOC_AR2316;
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break;
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case 0x86:
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default:
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ath25_soc = ATH25_SOC_AR2315;
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break;
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}
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ath25_board.devid = devid;
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/* Clear any lingering AHB errors */
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config = read_c0_config();
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write_c0_config(config & ~0x3);
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ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
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ar2315_rst_reg_read(AR2315_AHB_ERR1);
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ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
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_machine_restart = ar2315_restart;
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}
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#ifdef CONFIG_PCI_AR2315
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static struct resource ar2315_pci_res[] = {
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{
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.name = "ar2315-pci-ctrl",
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.flags = IORESOURCE_MEM,
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.start = AR2315_PCI_BASE,
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.end = AR2315_PCI_BASE + AR2315_PCI_SIZE - 1,
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},
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{
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.name = "ar2315-pci-ext",
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.flags = IORESOURCE_MEM,
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.start = AR2315_PCI_EXT_BASE,
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.end = AR2315_PCI_EXT_BASE + AR2315_PCI_EXT_SIZE - 1,
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},
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{
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.name = "ar2315-pci",
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.flags = IORESOURCE_IRQ,
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.start = AR2315_IRQ_LCBUS_PCI,
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.end = AR2315_IRQ_LCBUS_PCI,
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},
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};
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#endif
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void __init ar2315_arch_init(void)
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{
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unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
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AR2315_MISC_IRQ_UART0);
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ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
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#ifdef CONFIG_PCI_AR2315
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if (ath25_soc == ATH25_SOC_AR2315) {
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/* Reset PCI DMA logic */
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ar2315_rst_reg_mask(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
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msleep(20);
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ar2315_rst_reg_mask(AR2315_RESET, AR2315_RESET_PCIDMA, 0);
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msleep(20);
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/* Configure endians */
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ar2315_rst_reg_mask(AR2315_ENDIAN_CTL, 0, AR2315_CONFIG_PCIAHB |
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AR2315_CONFIG_PCIAHB_BRIDGE);
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/* Configure as PCI host with DMA */
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ar2315_rst_reg_write(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
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(AR2315_PCICLK_IN_FREQ_DIV_6 <<
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AR2315_PCICLK_DIV_S));
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ar2315_rst_reg_mask(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
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ar2315_rst_reg_mask(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK |
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AR2315_IF_MASK, AR2315_IF_PCI |
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AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
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(AR2315_IF_PCI_CLK_OUTPUT_CLK <<
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AR2315_IF_PCI_CLK_SHIFT));
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platform_device_register_simple("ar2315-pci", -1,
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ar2315_pci_res,
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ARRAY_SIZE(ar2315_pci_res));
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}
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#endif
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}
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