kernel_optimize_test/arch/sparc64/mm
David S. Miller a0663a79ad [SPARC64]: Fix TLB context allocation with SMT style shared TLBs.
The context allocation scheme we use depends upon there being a 1<-->1
mapping from cpu to physical TLB for correctness.  Chips like Niagara
break this assumption.

So what we do is notify all cpus with a cross call when the context
version number changes, and if necessary this makes them allocate
a valid context for the address space they are running at the time.

Stress tested with make -j1024, make -j2048, and make -j4096 kernel
builds on a 32-strand, 8 core, T2000 with 16GB of ram.

Signed-off-by: David S. Miller <davem@davemloft.net>
2006-03-20 01:14:00 -08:00
..
fault.c [SPARC64]: Log faulting vaddr when bogus kernel PC detected. 2006-03-20 01:12:38 -08:00
generic.c [SPARC64]: Deal with PTE layout differences in SUN4V. 2006-03-20 01:12:25 -08:00
hugetlbpage.c [PATCH] Hugepage consolidation 2005-06-21 18:46:15 -07:00
init.c [SPARC64]: Fix TLB context allocation with SMT style shared TLBs. 2006-03-20 01:14:00 -08:00
Makefile [SPARC64]: Move away from virtual page tables, part 1. 2006-03-20 01:11:13 -08:00
tlb.c [SPARC64]: Move away from virtual page tables, part 1. 2006-03-20 01:11:13 -08:00
tsb.c [SPARC64]: More TLB/TSB handling fixes. 2006-03-20 01:13:34 -08:00
ultra.S [SPARC64]: Fix comment typo in __flush_tlb_kernel_range. 2006-03-20 01:13:06 -08:00