forked from luck/tmp_suning_uos_patched
9c1f2a5dc2
The TI K3 AM65x and J721E family of SoCs have a new Mailbox IP that is based on the existing Mailbox IP present in OMAP architecture based SoCs. Each instance of the legacy OMAP Mailbox IP is now a single cluster within the newer Mailbox IP instance on K3 architecture based SoCs. A single K3 Mailbox IP instance has multiple clusters with each cluster providing the same functionality as the existing OMAP Mailbox IP. Reuse the existing OMAP Mailbox driver to extend the support for this newer IP present within the Main NavSS block on K3 SoCs. The K3 family of SoCs use 64-bit ARMv8 processors for running Linux, so the driver is also enhanced to deal with the differences between the 32-bit message payloads and the 64-bit pointers used by the client drivers. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
27 lines
689 B
C
27 lines
689 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* omap-mailbox: interprocessor communication module for OMAP
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*/
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#ifndef OMAP_MAILBOX_H
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#define OMAP_MAILBOX_H
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typedef uintptr_t mbox_msg_t;
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#define omap_mbox_message(data) (u32)(mbox_msg_t)(data)
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typedef int __bitwise omap_mbox_irq_t;
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#define IRQ_TX ((__force omap_mbox_irq_t) 1)
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#define IRQ_RX ((__force omap_mbox_irq_t) 2)
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struct mbox_chan;
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struct mbox_client;
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struct mbox_chan *omap_mbox_request_channel(struct mbox_client *cl,
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const char *chan_name);
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void omap_mbox_enable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq);
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void omap_mbox_disable_irq(struct mbox_chan *chan, omap_mbox_irq_t irq);
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#endif /* OMAP_MAILBOX_H */
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