Konstantin Porotchkin a45af6d3a9 clk: mvebu: cp110: add sdio clock to cp-110 system controller ... This commit updates the CP110 system controller driver to add the definition for a missing clock. The SDIO clock is dedicated driving the SDHCI interface and its frequency is 400MHz (2/5 of PLL source clock). The SDIO interface should be bound to this clock and not the core clock as in the older code. Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while the HW really supports up to 400 Mhz. This patch also fixes the NAND clock relationship documentation. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [gregory.clement@free-electrons.com: - use sdio instead of emmc to name the clock] Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>		2017-06-19 17:22:23 +02:00
..
at91
axis
axs10x
bcm
berlin
h8300
hisilicon
imx
ingenic
keystone
loongson1
mediatek
meson
microchip
mmp
mvebu	clk: mvebu: cp110: add sdio clock to cp-110 system controller	2017-06-19 17:22:23 +02:00
mxs
nxp
pistachio
pxa
qcom
renesas
rockchip
samsung
sirf
socfpga
spear
st
sunxi
sunxi-ng
tegra
ti
uniphier
ux500
versatile
x86
zte
zynq
clk-asm9260.c
clk-axi-clkgen.c
clk-axm5516.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gpio.c
clk-hi655x.c
clk-highbank.c
clk-max77686.c
clk-mb86s7x.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c
clk-scpi.c
clk-si514.c
clk-si570.c
clk-si5351.c
clk-si5351.h
clk-stm32f4.c
clk-tango4.c
clk-twl6040.c
clk-u300.c
clk-versaclock5.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c
clk.h
clkdev.c
Kconfig
Makefile