forked from luck/tmp_suning_uos_patched
f137e463b5
- Kconfig and Makefile changes
- arch/mips/sibyte/bcm1480/
- changes to sibyte common code to support 1480
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
166 lines
4.5 KiB
ArmAsm
166 lines
4.5 KiB
ArmAsm
/*
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* Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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* bcm1480_irq_handler() is the routine that is actually called when an
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* interrupt occurs. It is installed as the exception vector handler in
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* init_IRQ() in arch/mips/sibyte/bcm1480/irq.c
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*
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* In the handle we figure out which interrupts need handling, and use that
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* to call the dispatcher, which will take care of actually calling
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* registered handlers
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*
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* Note that we take care of all raised interrupts in one go at the handler.
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* This is more BSDish than the Indy code, and also, IMHO, more sane.
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*/
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#include <linux/config.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/sibyte/sb1250_defs.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/bcm1480_int.h>
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/*
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* What a pain. We have to be really careful saving the upper 32 bits of any
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* register across function calls if we don't want them trashed--since were
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* running in -o32, the calling routing never saves the full 64 bits of a
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* register across a function call. Being the interrupt handler, we're
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* guaranteed that interrupts are disabled during this code so we don't have
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* to worry about random interrupts blasting the high 32 bits.
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*/
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.text
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.set push
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.set noreorder
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.set noat
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.set mips64
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#.set mips4
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.align 5
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NESTED(bcm1480_irq_handler, PT_SIZE, sp)
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SAVE_ALL
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CLI
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#ifdef CONFIG_SIBYTE_BCM1480_PROF
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/* Set compare to count to silence count/compare timer interrupts */
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mfc0 t1, CP0_COUNT
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mtc0 t1, CP0_COMPARE /* pause to clear IP[7] bit of cause ? */
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#endif
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/* Read cause */
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mfc0 s0, CP0_CAUSE
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#ifdef CONFIG_SIBYTE_BCM1480_PROF
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/* Cpu performance counter interrupt is routed to IP[7] */
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andi t1, s0, CAUSEF_IP7
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beqz t1, 0f
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srl t1, s0, (CAUSEB_BD-2) /* Shift BD bit to bit 2 */
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and t1, t1, 0x4 /* mask to get just BD bit */
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#ifdef CONFIG_MIPS64
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dmfc0 a0, CP0_EPC
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daddu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
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#else
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mfc0 a0, CP0_EPC
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addu a0, a0, t1 /* a0 = EPC + (BD ? 4 : 0) */
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#endif
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jal sbprof_cpu_intr
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nop
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j ret_from_irq
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nop
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0:
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#endif
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/* Timer interrupt is routed to IP[4] */
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andi t1, s0, CAUSEF_IP4
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beqz t1, 1f
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nop
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jal bcm1480_timer_interrupt
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move a0, sp /* Pass the registers along */
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j ret_from_irq
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nop /* delay slot */
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1:
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#ifdef CONFIG_SMP
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/* Mailbox interrupt is routed to IP[3] */
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andi t1, s0, CAUSEF_IP3
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beqz t1, 2f
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nop
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jal bcm1480_mailbox_interrupt
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move a0, sp
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j ret_from_irq
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nop /* delay slot */
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2:
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#endif
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#ifdef CONFIG_KGDB
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/* KGDB (uart 1) interrupt is routed to IP[6] */
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andi t1, s0, CAUSEF_IP6
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beqz t1, 3f
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nop /* delay slot */
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jal bcm1480_kgdb_interrupt
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move a0, sp
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j ret_from_irq
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nop /* delay slot */
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3:
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#endif
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and t1, s0, CAUSEF_IP2
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beqz t1, 9f
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nop
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/*
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* Default...we've hit an IP[2] interrupt, which means we've got
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* to check the 1480 interrupt registers to figure out what to do
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* Need to detect which CPU we're on, now that smp_affinity is
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* supported.
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*/
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PTR_LA v0, CKSEG1 + A_BCM1480_IMR_CPU0_BASE
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#ifdef CONFIG_SMP
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lw t1, TI_CPU($28)
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sll t1, t1, BCM1480_IMR_REGISTER_SPACING_SHIFT
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addu v0, v0, t1
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#endif
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/* Read IP[2] status (get both high and low halves of status) */
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ld s0, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H(v0)
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ld s1, R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L(v0)
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move s2, zero /* intr number */
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li s3, 64
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beqz s0, 9f /* No interrupts. Return. */
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move a1, sp
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xori s4, s0, 1 /* if s0 (_H) == 1, it's a low intr, so... */
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movz s2, s3, s4 /* start the intr number at 64, and */
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movz s0, s1, s4 /* look at the low status value. */
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dclz s1, s0 /* Find the next interrupt. */
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dsubu a0, zero, s1
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daddiu a0, a0, 63
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jal do_IRQ
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daddu a0, a0, s2
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9: j ret_from_irq
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nop
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.set pop
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END(bcm1480_irq_handler)
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