forked from luck/tmp_suning_uos_patched
3cabf37f61
I don't know, if this new code boots, but at least it compiles. Someone should really test it. Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: Robert Richter <robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* Low-Level PCI Support for SGI Visual Workstation
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*
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* (c) 1999--2000 Martin Mares <mj@ucw.cz>
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <asm/setup.h>
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#include <asm/visws/cobalt.h>
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#include <asm/visws/lithium.h>
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#include "pci.h"
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static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
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static void pci_visws_disable_irq(struct pci_dev *dev) { }
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/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
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/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
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/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
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unsigned int pci_bus0, pci_bus1;
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static inline u8 bridge_swizzle(u8 pin, u8 slot)
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{
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return (((pin - 1) + slot) % 4) + 1;
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}
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static u8 __init visws_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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u8 pin = *pinp;
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while (dev->bus->self) { /* Move up the chain of bridges. */
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pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
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dev = dev->bus->self;
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}
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*pinp = pin;
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return PCI_SLOT(dev->devfn);
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}
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static int __init visws_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq, bus = dev->bus->number;
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pin--;
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/* Nothing useful at PIIX4 pin 1 */
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if (bus == pci_bus0 && slot == 4 && pin == 0)
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return -1;
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/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
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if (bus == pci_bus0 && slot == 4 && pin == 3) {
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irq = CO_IRQ(CO_APIC_PIIX4_USB);
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goto out;
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}
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/* First pin spread down 1 APIC entry per slot */
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if (pin == 0) {
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irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
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CO_APIC_PCIA_BASE0) + slot);
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goto out;
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}
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/* lines 1,2,3 from any slot is shared in this twirly pattern */
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if (bus == pci_bus1) {
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/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
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irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
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} else { /* bus == pci_bus0 */
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/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
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if (slot == 0)
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slot = 3; /* same pattern */
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irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
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}
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out:
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printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
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return irq;
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}
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void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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int __init pci_visws_init(void)
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{
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if (!is_visws_box())
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return -1;
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pcibios_enable_irq = &pci_visws_enable_irq;
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pcibios_disable_irq = &pci_visws_disable_irq;
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/* The VISWS supports configuration access type 1 only */
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pci_probe = (pci_probe | PCI_PROBE_CONF1) &
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~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
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pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
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pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
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printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
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"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
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raw_pci_ops = &pci_direct_conf1;
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pci_scan_bus_with_sysdata(pci_bus0);
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pci_scan_bus_with_sysdata(pci_bus1);
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pci_fixup_irqs(visws_swizzle, visws_map_irq);
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pcibios_resource_survey();
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return 0;
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}
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