forked from luck/tmp_suning_uos_patched
7232398abc
This commit converts the PMC support code to a platform driver. Because the boot process needs to call into this driver very early, also set up a minimal environment via an early initcall. Signed-off-by: Thierry Reding <treding@nvidia.com>
401 lines
8.5 KiB
C
401 lines
8.5 KiB
C
/*
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* CPU complex suspend & resume functions for Tegra SoCs
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*
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* Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk/tegra.h>
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#include <linux/cpumask.h>
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#include <linux/cpu_pm.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/suspend.h>
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#include <soc/tegra/fuse.h>
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#include <soc/tegra/pm.h>
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#include <soc/tegra/pmc.h>
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#include <asm/cacheflush.h>
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#include <asm/idmap.h>
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#include <asm/proc-fns.h>
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#include <asm/smp_plat.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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#include "flowctrl.h"
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#include "iomap.h"
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#include "pm.h"
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#include "reset.h"
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#include "sleep.h"
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#ifdef CONFIG_PM_SLEEP
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static DEFINE_SPINLOCK(tegra_lp2_lock);
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static u32 iram_save_size;
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static void *iram_save_addr;
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struct tegra_lp1_iram tegra_lp1_iram;
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void (*tegra_tear_down_cpu)(void);
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void (*tegra_sleep_core_finish)(unsigned long v2p);
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static int (*tegra_sleep_func)(unsigned long v2p);
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static void tegra_tear_down_cpu_init(void)
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{
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
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tegra_tear_down_cpu = tegra20_tear_down_cpu;
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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tegra_tear_down_cpu = tegra30_tear_down_cpu;
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break;
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}
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}
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/*
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* restore_cpu_complex
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*
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* restores cpu clock setting, clears flow controller
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*
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* Always called on CPU 0.
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*/
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static void restore_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Restore the CPU clock settings */
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tegra_cpu_clock_resume();
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flowctrl_cpu_suspend_exit(cpu);
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}
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/*
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* suspend_cpu_complex
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*
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* saves pll state for use by restart_plls, prepares flow controller for
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* transition to suspend state
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*
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* Must always be called on cpu 0.
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*/
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static void suspend_cpu_complex(void)
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{
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int cpu = smp_processor_id();
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BUG_ON(cpu != 0);
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#ifdef CONFIG_SMP
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cpu = cpu_logical_map(cpu);
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#endif
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/* Save the CPU clock settings */
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tegra_cpu_clock_suspend();
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flowctrl_cpu_suspend_enter(cpu);
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}
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void tegra_clear_cpu_in_lp2(void)
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{
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int phy_cpu_id = cpu_logical_map(smp_processor_id());
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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spin_lock(&tegra_lp2_lock);
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BUG_ON(!(*cpu_in_lp2 & BIT(phy_cpu_id)));
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*cpu_in_lp2 &= ~BIT(phy_cpu_id);
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spin_unlock(&tegra_lp2_lock);
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}
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bool tegra_set_cpu_in_lp2(void)
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{
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int phy_cpu_id = cpu_logical_map(smp_processor_id());
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bool last_cpu = false;
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cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
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u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
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spin_lock(&tegra_lp2_lock);
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BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
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*cpu_in_lp2 |= BIT(phy_cpu_id);
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if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
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last_cpu = true;
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else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1)
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tegra20_cpu_set_resettable_soon();
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spin_unlock(&tegra_lp2_lock);
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return last_cpu;
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}
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int tegra_cpu_do_idle(void)
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{
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return cpu_do_idle();
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}
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static int tegra_sleep_cpu(unsigned long v2p)
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{
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setup_mm_for_reboot();
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tegra_sleep_cpu_finish(v2p);
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/* should never here */
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BUG();
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return 0;
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}
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static void tegra_pm_set(enum tegra_suspend_mode mode)
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{
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u32 value;
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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case TEGRA30:
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break;
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default:
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/* Turn off CRAIL */
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value = flowctrl_read_cpu_csr(0);
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value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
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value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
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flowctrl_write_cpu_csr(0, value);
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break;
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}
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tegra_pmc_enter_suspend_mode(mode);
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}
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void tegra_idle_lp2_last(void)
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{
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tegra_pm_set(TEGRA_SUSPEND_LP2);
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cpu_cluster_pm_enter();
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suspend_cpu_complex();
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
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restore_cpu_complex();
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cpu_cluster_pm_exit();
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}
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enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
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enum tegra_suspend_mode mode)
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{
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/*
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* The Tegra devices support suspending to LP1 or lower currently.
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*/
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if (mode > TEGRA_SUSPEND_LP1)
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return TEGRA_SUSPEND_LP1;
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return mode;
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}
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static int tegra_sleep_core(unsigned long v2p)
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{
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setup_mm_for_reboot();
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tegra_sleep_core_finish(v2p);
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/* should never here */
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BUG();
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return 0;
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}
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/*
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* tegra_lp1_iram_hook
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*
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* Hooking the address of LP1 reset vector and SDRAM self-refresh code in
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* SDRAM. These codes not be copied to IRAM in this fuction. We need to
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* copy these code to IRAM before LP0/LP1 suspend and restore the content
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* of IRAM after resume.
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*/
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static bool tegra_lp1_iram_hook(void)
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{
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
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tegra20_lp1_iram_hook();
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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tegra30_lp1_iram_hook();
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break;
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default:
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break;
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}
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if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
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return false;
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iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
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iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
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if (!iram_save_addr)
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return false;
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return true;
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}
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static bool tegra_sleep_core_init(void)
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{
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switch (tegra_get_chip_id()) {
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case TEGRA20:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
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tegra20_sleep_core_init();
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break;
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case TEGRA30:
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case TEGRA114:
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case TEGRA124:
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if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
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IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
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tegra30_sleep_core_init();
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break;
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default:
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break;
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}
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if (!tegra_sleep_core_finish)
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return false;
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return true;
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}
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static void tegra_suspend_enter_lp1(void)
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{
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/* copy the reset vector & SDRAM shutdown code into IRAM */
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memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
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iram_save_size);
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memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA),
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tegra_lp1_iram.start_addr, iram_save_size);
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*((u32 *)tegra_cpu_lp1_mask) = 1;
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}
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static void tegra_suspend_exit_lp1(void)
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{
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/* restore IRAM */
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memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr,
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iram_save_size);
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*(u32 *)tegra_cpu_lp1_mask = 0;
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}
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static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
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[TEGRA_SUSPEND_NONE] = "none",
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[TEGRA_SUSPEND_LP2] = "LP2",
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[TEGRA_SUSPEND_LP1] = "LP1",
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[TEGRA_SUSPEND_LP0] = "LP0",
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};
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static int tegra_suspend_enter(suspend_state_t state)
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{
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enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
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if (WARN_ON(mode < TEGRA_SUSPEND_NONE ||
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mode >= TEGRA_MAX_SUSPEND_MODE))
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return -EINVAL;
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pr_info("Entering suspend state %s\n", lp_state[mode]);
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tegra_pm_set(mode);
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local_fiq_disable();
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suspend_cpu_complex();
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switch (mode) {
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case TEGRA_SUSPEND_LP1:
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tegra_suspend_enter_lp1();
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break;
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case TEGRA_SUSPEND_LP2:
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tegra_set_cpu_in_lp2();
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break;
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default:
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break;
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}
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cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
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switch (mode) {
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case TEGRA_SUSPEND_LP1:
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tegra_suspend_exit_lp1();
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break;
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case TEGRA_SUSPEND_LP2:
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tegra_clear_cpu_in_lp2();
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break;
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default:
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break;
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}
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restore_cpu_complex();
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local_fiq_enable();
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return 0;
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}
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static const struct platform_suspend_ops tegra_suspend_ops = {
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.valid = suspend_valid_only_mem,
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.enter = tegra_suspend_enter,
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};
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void __init tegra_init_suspend(void)
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{
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enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
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if (mode == TEGRA_SUSPEND_NONE)
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return;
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tegra_tear_down_cpu_init();
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if (mode >= TEGRA_SUSPEND_LP1) {
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if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
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pr_err("%s: unable to allocate memory for SDRAM"
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"self-refresh -- LP0/LP1 unavailable\n",
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__func__);
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tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
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mode = TEGRA_SUSPEND_LP2;
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}
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}
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/* set up sleep function for cpu_suspend */
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switch (mode) {
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case TEGRA_SUSPEND_LP1:
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tegra_sleep_func = tegra_sleep_core;
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break;
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case TEGRA_SUSPEND_LP2:
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tegra_sleep_func = tegra_sleep_cpu;
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break;
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default:
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break;
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}
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suspend_set_ops(&tegra_suspend_ops);
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}
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#endif
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