kernel_optimize_test/arch/mips/mti-malta
Andrew Bresticker a669efc4a3 MIPS: Add hook to get C0 performance counter interrupt
The hardware perf event driver and oprofile interpret the global
cp0_perfcount_irq differently: in the hardware perf event driver
it is an offset from MIPS_CPU_IRQ_BASE and in oprofile it is the
actual IRQ number.  This still works most of the time since
MIPS_CPU_IRQ_BASE is usually 0, but is clearly wrong.  Since the
performance counter interrupt may vary from platform to platform
like the C0 timer interrupt, add the optional get_c0_perfcount_int
hook which returns the IRQ number of the performance counter.
The hook should return < 0 if the performance counter interrupt is
shared with the timer.  If the hook is not present, the CPU vector
reported in C0_IntCtl (cp0_perfcount_irq) is used.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
Tested-by: Qais Yousef <qais.yousef@imgtec.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
Cc: Markos Chandras <markos.chandras@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Qais Yousef <qais.yousef@imgtec.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7805/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:44:53 +01:00
..
Makefile MIPS: Malta: Do not build the malta-amon.c file if CMP is not enabled 2014-10-23 20:05:55 +02:00
malta-amon.c
malta-display.c
malta-init.c MIPS: MT: Remove SMTC support 2014-05-24 00:07:01 +02:00
malta-int.c MIPS: Malta: Fix dispatching of GIC interrupts 2014-08-02 00:06:41 +02:00
malta-memory.c MIPS: Malta: Improve system memory detection for '{e, }memsize' >= 2G 2014-08-19 13:30:47 +02:00
malta-platform.c
malta-pm.c MIPS: Malta: add suspend state entry code 2014-05-30 21:01:09 +02:00
malta-reset.c MIPS: Malta: support powering down 2014-05-30 21:01:09 +02:00
malta-setup.c MIPS: MT: Remove SMTC support 2014-05-24 00:07:01 +02:00
malta-time.c MIPS: Add hook to get C0 performance counter interrupt 2014-11-24 07:44:53 +01:00
Platform