forked from luck/tmp_suning_uos_patched
f9c6a655a9
The original device tree binding for this driver, from Viresh Kumar unfortunately conflicted with the generic DMA binding, and did not allow to completely seperate slave device configuration from the controller. This is an attempt to replace it with an implementation of the generic binding, but it is currently completely untested, because I do not have any hardware with this particular controller. The patch applies on top of the slave-dma tree, which contains both the base support for the generic DMA binding, as well as the earlier attempt from Viresh. Both of these are currently not merged upstream however. This version incorporates feedback from Viresh Kumar, Andy Shevchenko and Russell King. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Vinod Koul <vinod.koul@linux.intel.com> Cc: devicetree-discuss@lists.ozlabs.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
115 lines
3.8 KiB
C
115 lines
3.8 KiB
C
/*
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* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
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* AVR32 systems.)
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*
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* Copyright (C) 2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DW_DMAC_H
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#define DW_DMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device. Depricated.
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* @bus_id: name of this device channel, not just a device name since
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* devices may have more than one channel e.g. "foo_tx"
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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* @src_master: src master for transfers on allocated channel.
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* @dst_master: dest master for transfers on allocated channel.
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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u32 cfg_hi;
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u32 cfg_lo;
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u8 src_master;
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u8 dst_master;
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};
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @is_private: The device channels should be marked as private and not for
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* by the general purpose DMA channel allocator.
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* @chan_allocation_order: Allocate channels starting from 0 or 7
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* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
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* @block_size: Maximum block size supported by the controller
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* @nr_masters: Number of AHB masters supported by the controller
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* @data_width: Maximum data width supported by hardware per AHB master
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* (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
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* @sd: slave specific data. Used for configuring channels
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* @sd_count: count of slave data structures passed.
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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bool is_private;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
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unsigned char chan_priority;
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unsigned short block_size;
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unsigned char nr_masters;
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unsigned char data_width[4];
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};
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/* bursts size */
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enum dw_dma_msize {
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DW_DMA_MSIZE_1,
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DW_DMA_MSIZE_4,
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DW_DMA_MSIZE_8,
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DW_DMA_MSIZE_16,
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DW_DMA_MSIZE_32,
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DW_DMA_MSIZE_64,
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DW_DMA_MSIZE_128,
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DW_DMA_MSIZE_256,
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};
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/* Platform-configurable bits in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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#define DWC_CFGH_DST_PER(x) ((x) << 11)
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/* Platform-configurable bits in CFG_LO */
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#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
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#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
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#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
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#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
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#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
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#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
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#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
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#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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/* DMA API extensions */
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struct dw_cyclic_desc {
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struct dw_desc **desc;
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unsigned long periods;
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void (*period_callback)(void *param);
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void *period_callback_param;
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};
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struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len, size_t period_len,
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enum dma_transfer_direction direction);
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void dw_dma_cyclic_free(struct dma_chan *chan);
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int dw_dma_cyclic_start(struct dma_chan *chan);
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void dw_dma_cyclic_stop(struct dma_chan *chan);
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dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
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dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
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#endif /* DW_DMAC_H */
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