forked from luck/tmp_suning_uos_patched
59018b6d2a
Once upon a time, the MTD repository was using CVS. This patch therefore removes all usages of the no longer updated CVS keywords from the MTD code. This also includes code that printed them to the user. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
152 lines
5.6 KiB
C
152 lines
5.6 KiB
C
/*
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* drivers/mtd/nandids.c
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*
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* Copyright (C) 2002 Thomas Gleixner (tglx@linutronix.de)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/module.h>
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#include <linux/mtd/nand.h>
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/*
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* Chip ID list
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*
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* Name. ID code, pagesize, chipsize in MegaByte, eraseblock size,
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* options
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*
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* Pagesize; 0, 256, 512
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* 0 get this information from the extended chip ID
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+ 256 256 Byte page size
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* 512 512 Byte page size
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*/
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struct nand_flash_dev nand_flash_ids[] = {
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#ifdef CONFIG_MTD_NAND_MUSEUM_IDS
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{"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
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{"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
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{"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
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{"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
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{"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
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{"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
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{"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
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{"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
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{"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
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{"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
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{"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
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{"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
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{"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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{"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
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#endif
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{"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
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{"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
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{"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
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{"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
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{"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
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{"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
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{"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
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{"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
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{"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
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{"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
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{"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
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/*
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* These are the new chips with large page size. The pagesize and the
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* erasesize is determined from the extended id bytes
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*/
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#define LP_OPTIONS (NAND_SAMSUNG_LP_OPTIONS | NAND_NO_READRDY | NAND_NO_AUTOINCR)
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#define LP_OPTIONS16 (LP_OPTIONS | NAND_BUSWIDTH_16)
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/*512 Megabit */
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{"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
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{"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
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{"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
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{"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
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/* 1 Gigabit */
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{"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
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{"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
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{"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
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{"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
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/* 2 Gigabit */
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{"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
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{"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
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{"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
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{"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
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/* 4 Gigabit */
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{"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
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{"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
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{"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
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{"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
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/* 8 Gigabit */
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{"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
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{"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
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{"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
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{"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
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/* 16 Gigabit */
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{"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
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{"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
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{"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
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{"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
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/*
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* Renesas AND 1 Gigabit. Those chips do not support extended id and
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* have a strange page/block layout ! The chosen minimum erasesize is
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* 4 * 2 * 2048 = 16384 Byte, as those chips have an array of 4 page
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* planes 1 block = 2 pages, but due to plane arrangement the blocks
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* 0-3 consists of page 0 + 4,1 + 5, 2 + 6, 3 + 7 Anyway JFFS2 would
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* increase the eraseblock size so we chose a combined one which can be
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* erased in one go There are more speed improvements for reads and
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* writes possible, but not implemented now
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*/
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{"AND 128MiB 3,3V 8-bit", 0x01, 2048, 128, 0x4000,
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NAND_IS_AND | NAND_NO_AUTOINCR |NAND_NO_READRDY | NAND_4PAGE_ARRAY |
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BBT_AUTO_REFRESH
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},
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{NULL,}
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};
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/*
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* Manufacturer ID list
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*/
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struct nand_manufacturers nand_manuf_ids[] = {
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{NAND_MFR_TOSHIBA, "Toshiba"},
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{NAND_MFR_SAMSUNG, "Samsung"},
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{NAND_MFR_FUJITSU, "Fujitsu"},
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{NAND_MFR_NATIONAL, "National"},
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{NAND_MFR_RENESAS, "Renesas"},
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{NAND_MFR_STMICRO, "ST Micro"},
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{NAND_MFR_HYNIX, "Hynix"},
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{NAND_MFR_MICRON, "Micron"},
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{NAND_MFR_AMD, "AMD"},
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{0x0, "Unknown"}
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};
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EXPORT_SYMBOL(nand_manuf_ids);
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EXPORT_SYMBOL(nand_flash_ids);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
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MODULE_DESCRIPTION("Nand device & manufacturer IDs");
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