Lu Baolu a9bc9c9320 iommu/vt-d: Fix unaligned addresses for intel_flush_svm_range_dev() ... commit 2d6ffc63f12417b979955a5b22ad9a76d2af5de9 upstream. The VT-d hardware will ignore those Addr bits which have been masked by the AM field in the PASID-based-IOTLB invalidation descriptor. As the result, if the starting address in the descriptor is not aligned with the address mask, some IOTLB caches might not invalidate. Hence people will see below errors. [ 1093.704661] dmar_fault: 29 callbacks suppressed [ 1093.704664] DMAR: DRHD: handling fault status reg 3 [ 1093.712738] DMAR: [DMA Read] Request device [7a:02.0] PASID 2 fault addr 7f81c968d000 [fault reason 113] SM: Present bit in first-level paging entry is clear Fix this by using aligned address for PASID-based-IOTLB invalidation. Fixes: 1c4f88b7f1 ("iommu/vt-d: Shared virtual address in scalable mode") Reported-and-tested-by: Guo Kaijie <Kaijie.Guo@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Link: https://lore.kernel.org/r/20201231005323.2178523-2-baolu.lu@linux.intel.com Signed-off-by: Will Deacon <will@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2021-01-19 18:27:33 +01:00
..
amd
arm	iommu/arm-smmu-qcom: Initialize SCTLR of the bypass context	2021-01-17 14:16:53 +01:00
intel	iommu/vt-d: Fix unaligned addresses for intel_flush_svm_range_dev()	2021-01-19 18:27:33 +01:00
dma-iommu.c
exynos-iommu.c
fsl_pamu_domain.c
fsl_pamu_domain.h
fsl_pamu.c
fsl_pamu.h
hyperv-iommu.c
io-pgtable-arm-v7s.c
io-pgtable-arm.c
io-pgtable-arm.h
io-pgtable.c
ioasid.c
iommu-debugfs.c
iommu-sysfs.c
iommu-traces.c
iommu.c
iova.c
ipmmu-vmsa.c
irq_remapping.c
irq_remapping.h
Kconfig
Makefile
msm_iommu_hw-8xxx.h
msm_iommu.c
msm_iommu.h
mtk_iommu_v1.c
mtk_iommu.c
mtk_iommu.h
of_iommu.c
omap-iommu-debug.c
omap-iommu.c
omap-iommu.h
omap-iopgtable.h
rockchip-iommu.c
s390-iommu.c
sun50i-iommu.c
tegra-gart.c
tegra-smmu.c
virtio-iommu.c